Refactored coherence as member rather than trait. MI and MEI protocols.

rocket/src/main/scala/coherence.scala

@@ -50,7 +50,7 @@ object cpuCmdToRW {
   }
 }
 
-trait CoherencePolicy {
+abstract class CoherencePolicy {
   def isHit (cmd: Bits, state: UFix): Bool
   def isValid (state: UFix): Bool
 
@@ -72,9 +72,10 @@ trait CoherencePolicy {
 
   def newProbeReply (incoming: ProbeRequest, state: UFix): ProbeReply
 
-  def hasData (reply: ProbeReply): Bool
-  def hasData (init: TransactionInit): Bool
-  def hasData (reply: TransactionReply): Bool
+  def messageHasData (reply: ProbeReply): Bool
+  def messageHasData (init: TransactionInit): Bool
+  def messageHasData (reply: TransactionReply): Bool
+  def messageUpdatesDataArray (reply: TransactionReply): Bool
 
   def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool
   def getTransactionReplyType(x_type: UFix, count: UFix): Bits
@@ -84,7 +85,14 @@ trait CoherencePolicy {
   def needsAckReply(x_type: UFix, global_state: UFix): Bool
 }
 
-trait IncoherentPolicy extends CoherencePolicy {
+trait UncachedTransactions {
+  def getTransactionInitTypeOnUncachedRead(): UFix
+  def getTransactionInitTypeOnUncachedWrite(): UFix
+}
+
+abstract class CoherencePolicyWithUncached extends CoherencePolicy with UncachedTransactions
+
+abstract class IncoherentPolicy extends CoherencePolicy {
   // UNIMPLEMENTED
   def newStateOnProbeRequest(incoming: ProbeRequest, state: UFix): Bits = state
   def newProbeReply (incoming: ProbeRequest, state: UFix): ProbeReply = { 
@@ -93,7 +101,7 @@ trait IncoherentPolicy extends CoherencePolicy {
     reply.global_xact_id := UFix(0)
     reply
   }
-  def hasData (reply: ProbeReply) = Bool(false)
+  def messageHasData (reply: ProbeReply) = Bool(false)
   def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool = Bool(false)
   def getTransactionReplyType(x_type: UFix, count: UFix): Bits = Bits(0)
   def getProbeRequestType(x_type: UFix, global_state: UFix): UFix = UFix(0)
@@ -102,7 +110,7 @@ trait IncoherentPolicy extends CoherencePolicy {
   def needsAckReply(x_type: UFix, global_state: UFix): Bool = Bool(false)
 }
 
-trait ThreeStateIncoherence extends IncoherentPolicy {
+class ThreeStateIncoherence extends IncoherentPolicy {
   val tileInvalid :: tileClean :: tileDirty :: Nil = Enum(3){ UFix() }
   val xactInitReadClean :: xactInitReadDirty :: xactInitWriteback :: Nil = Enum(3){ UFix() }
   val xactReplyData :: xactReplyAck :: Nil = Enum(2){ UFix() }
@@ -141,11 +149,256 @@ trait ThreeStateIncoherence extends IncoherentPolicy {
   def getTransactionInitTypeOnCacheControl(cmd: Bits): Bits = xactInitWriteback //TODO
   def getTransactionInitTypeOnWriteback(): Bits = xactInitWriteback
 
-  def hasData (init: TransactionInit): Bool = (init.x_type === xactInitWriteback)
-  def hasData (reply: TransactionReply) = (reply.x_type === xactReplyData)
+  def messageHasData (init: TransactionInit): Bool = (init.x_type === xactInitWriteback)
+  def messageHasData (reply: TransactionReply) = (reply.x_type === xactReplyData)
+  def messageUpdatesDataArray (reply: TransactionReply) = (reply.x_type === xactReplyData)
 }
 
-trait FourStateCoherence extends CoherencePolicy {
+class TwoStateCoherence extends CoherencePolicyWithUncached {
+
+  val tileInvalid :: tileValid :: Nil = Enum(2){ UFix() }
+  val globalInvalid :: globalValid :: Nil = Enum(2){ UFix() }
+
+  val xactInitReadExclusive :: xactInitReadUncached :: xactInitWriteUncached :: Nil = Enum(3){ UFix() }
+  val xactReplyReadExclusive :: xactReplyReadUncached :: xactReplyWriteUncached :: Nil = Enum(3){ UFix() } 
+  val probeReqInvalidate :: probeReqCopy :: Nil = Enum(2){ UFix() }
+  val probeRepInvalidateData :: probeRepCopyData :: probeRepInvalidateAck :: probeRepCopyAck :: Nil = Enum(4){ UFix() }
+
+  def isHit (cmd: Bits, state: UFix): Bool = state != tileInvalid
+  def isValid (state: UFix): Bool = state != tileInvalid
+
+  def needsTransactionOnSecondaryMiss(cmd: Bits, outstanding: TransactionInit): Bool = (outstanding.x_type != xactInitReadExclusive)
+  def needsTransactionOnCacheControl(cmd: Bits, state: UFix): Bool = {
+    MuxLookup(cmd, (state === tileValid), Array(
+      M_INV -> (state === tileValid),
+      M_CLN -> (state === tileValid)
+    ))
+  }
+  def needsWriteback (state: UFix): Bool = {
+    needsTransactionOnCacheControl(M_INV, state)
+  }
+
+  def newStateOnHit(cmd: Bits, state: UFix): UFix = state
+  def newStateOnCacheControl(cmd: Bits) = {
+    MuxLookup(cmd, tileInvalid, Array(
+      M_INV -> tileInvalid,
+      M_CLN -> tileValid
+    ))
+  }
+  def newStateOnWriteback() = newStateOnCacheControl(M_INV)
+  def newStateOnFlush() = newStateOnCacheControl(M_INV)
+  def newStateOnTransactionReply(incoming: TransactionReply, outstanding: TransactionInit): UFix = {
+    MuxLookup(incoming.x_type, tileInvalid, Array(
+      xactReplyReadExclusive -> tileValid,
+      xactReplyReadUncached  -> tileInvalid,
+      xactReplyWriteUncached -> tileInvalid
+    ))
+  } 
+  def newStateOnProbeRequest(incoming: ProbeRequest, state: UFix): Bits = {
+    MuxLookup(incoming.p_type, state, Array(
+      probeReqInvalidate -> tileInvalid,
+      probeReqCopy       -> state
+    ))
+  }
+
+  def getTransactionInitTypeOnUncachedRead() = xactInitReadUncached 
+  def getTransactionInitTypeOnUncachedWrite() = xactInitWriteUncached 
+  def getTransactionInitTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = xactInitReadExclusive
+  def getTransactionInitTypeOnSecondaryMiss(cmd: Bits, state: UFix, outstanding: TransactionInit): UFix = xactInitReadExclusive
+  def getTransactionInitTypeOnCacheControl(cmd: Bits): Bits = xactInitWriteUncached
+  def getTransactionInitTypeOnWriteback(): Bits = getTransactionInitTypeOnCacheControl(M_INV)
+
+  def newProbeReply (incoming: ProbeRequest, state: UFix): ProbeReply = {
+    val reply = Wire() { new ProbeReply() }
+    val with_data = MuxLookup(incoming.p_type, probeRepInvalidateData, Array(
+      probeReqInvalidate -> probeRepInvalidateData,
+      probeReqCopy       -> probeRepCopyData
+    ))
+    val without_data = MuxLookup(incoming.p_type, probeRepInvalidateAck, Array(
+      probeReqInvalidate -> probeRepInvalidateAck,
+      probeReqCopy       -> probeRepCopyAck
+    ))
+    reply.p_type := Mux(needsWriteback(state), with_data, without_data)
+    reply.global_xact_id := incoming.global_xact_id
+    reply
+  }
+
+  def messageHasData (reply: ProbeReply): Bool = {
+    (reply.p_type === probeRepInvalidateData ||
+     reply.p_type === probeRepCopyData)
+  }
+  def messageHasData (init: TransactionInit): Bool = {
+    (init.x_type === xactInitWriteUncached)
+  }
+  def messageHasData (reply: TransactionReply): Bool = {
+    (reply.x_type != xactReplyWriteUncached)
+  }
+  def messageUpdatesDataArray (reply: TransactionReply): Bool = {
+    (reply.x_type === xactReplyReadExclusive)
+  }
+
+  def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool = (addr1 === addr2)
+
+  def getTransactionReplyType(x_type: UFix, count: UFix): Bits = {
+    MuxLookup(x_type, xactReplyReadUncached, Array(
+      xactInitReadExclusive -> xactReplyReadExclusive,
+      xactInitReadUncached  -> xactReplyReadUncached,
+      xactInitWriteUncached -> xactReplyWriteUncached
+    ))
+  }
+
+  def getProbeRequestType(x_type: UFix, global_state: UFix): UFix = {
+    MuxLookup(x_type, probeReqCopy, Array(
+      xactInitReadExclusive -> probeReqInvalidate, 
+      xactInitReadUncached -> probeReqCopy, 
+      xactInitWriteUncached -> probeReqInvalidate
+    ))
+  }
+
+  def needsMemRead(x_type: UFix, global_state: UFix): Bool = {
+      (x_type != xactInitWriteUncached)
+  }
+  def needsMemWrite(x_type: UFix, global_state: UFix): Bool = {
+      (x_type === xactInitWriteUncached)
+  }
+  def needsAckReply(x_type: UFix, global_state: UFix): Bool = {
+      (x_type === xactInitWriteUncached)
+  }
+}
+
+class ThreeStateCoherence extends CoherencePolicyWithUncached { //MEI
+
+  val tileInvalid :: tileExclusiveClean :: tileExclusiveDirty :: Nil = Enum(3){ UFix() }
+  val globalInvalid :: globalExclusiveClean :: Nil = Enum(2){ UFix() }
+
+  val xactInitReadExclusiveClean :: xactInitReadExclusiveDirty :: xactInitReadUncached :: xactInitWriteUncached :: Nil = Enum(4){ UFix() }
+  val xactReplyReadExclusive :: xactReplyReadUncached :: xactReplyWriteUncached :: xactReplyReadExclusiveAck :: Nil = Enum(4){ UFix() } 
+  val probeReqInvalidate :: probeReqDowngrade :: probeReqCopy :: Nil = Enum(3){ UFix() }
+  val probeRepInvalidateData :: probeRepDowngradeData :: probeRepCopyData :: probeRepInvalidateAck :: probeRepDowngradeAck :: probeRepCopyAck :: Nil = Enum(6){ UFix() }
+
+  def isHit (cmd: Bits, state: UFix): Bool = state != tileInvalid
+  def isValid (state: UFix): Bool = state != tileInvalid
+
+  def needsTransactionOnSecondaryMiss(cmd: Bits, outstanding: TransactionInit): Bool = {
+    val (read, write) = cpuCmdToRW(cmd)
+    (read && (outstanding.x_type === xactInitReadUncached || outstanding.x_type === xactInitWriteUncached)) ||
+      (write && (outstanding.x_type != xactInitReadExclusiveDirty))
+  }
+  def needsTransactionOnCacheControl(cmd: Bits, state: UFix): Bool = {
+    MuxLookup(cmd, (state === tileExclusiveDirty), Array(
+      M_INV -> (state === tileExclusiveDirty),
+      M_CLN -> (state === tileExclusiveDirty)
+    ))
+  }
+  def needsWriteback (state: UFix): Bool = {
+    needsTransactionOnCacheControl(M_INV, state)
+  }
+
+  def newStateOnHit(cmd: Bits, state: UFix): UFix = { 
+    val (read, write) = cpuCmdToRW(cmd)
+    Mux(write, tileExclusiveDirty, state)
+  }
+  def newStateOnCacheControl(cmd: Bits) = {
+    MuxLookup(cmd, tileInvalid, Array(
+      M_INV -> tileInvalid,
+      M_CLN -> tileExclusiveClean
+    ))
+  }
+  def newStateOnWriteback() = newStateOnCacheControl(M_INV)
+  def newStateOnFlush() = newStateOnCacheControl(M_INV)
+  def newStateOnTransactionReply(incoming: TransactionReply, outstanding: TransactionInit): UFix = {
+    MuxLookup(incoming.x_type, tileInvalid, Array(
+      xactReplyReadExclusive  -> Mux(outstanding.x_type === xactInitReadExclusiveDirty, tileExclusiveDirty, tileExclusiveClean),
+      xactReplyReadExclusiveAck -> tileExclusiveDirty, 
+      xactReplyReadUncached -> tileInvalid,
+      xactReplyWriteUncached -> tileInvalid
+    ))
+  } 
+  def newStateOnProbeRequest(incoming: ProbeRequest, state: UFix): Bits = {
+    MuxLookup(incoming.p_type, state, Array(
+      probeReqInvalidate -> tileInvalid,
+      probeReqDowngrade  -> tileExclusiveClean,
+      probeReqCopy       -> state
+    ))
+  }
+
+  def getTransactionInitTypeOnUncachedRead() = xactInitReadUncached 
+  def getTransactionInitTypeOnUncachedWrite() = xactInitWriteUncached 
+  def getTransactionInitTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = {
+    val (read, write) = cpuCmdToRW(cmd)
+    Mux(write, xactInitReadExclusiveDirty, xactInitReadExclusiveClean)
+  }
+  def getTransactionInitTypeOnSecondaryMiss(cmd: Bits, state: UFix, outstanding: TransactionInit): UFix = {
+    val (read, write) = cpuCmdToRW(cmd)
+    Mux(write, xactInitReadExclusiveDirty, outstanding.x_type)
+  }
+  def getTransactionInitTypeOnCacheControl(cmd: Bits): Bits = xactInitWriteUncached
+  def getTransactionInitTypeOnWriteback(): Bits = getTransactionInitTypeOnCacheControl(M_INV)
+
+  def newProbeReply (incoming: ProbeRequest, state: UFix): ProbeReply = {
+    val reply = Wire() { new ProbeReply() }
+    val with_data = MuxLookup(incoming.p_type, probeRepInvalidateData, Array(
+      probeReqInvalidate -> probeRepInvalidateData,
+      probeReqDowngrade  -> probeRepDowngradeData,
+      probeReqCopy       -> probeRepCopyData
+    ))
+    val without_data = MuxLookup(incoming.p_type, probeRepInvalidateAck, Array(
+      probeReqInvalidate -> probeRepInvalidateAck,
+      probeReqDowngrade  -> probeRepDowngradeAck,
+      probeReqCopy       -> probeRepCopyAck
+    ))
+    reply.p_type := Mux(needsWriteback(state), with_data, without_data)
+    reply.global_xact_id := incoming.global_xact_id
+    reply
+  }
+
+  def messageHasData (reply: ProbeReply): Bool = {
+    (reply.p_type === probeRepInvalidateData ||
+     reply.p_type === probeRepDowngradeData ||
+     reply.p_type === probeRepCopyData)
+  }
+  def messageHasData (init: TransactionInit): Bool = {
+    (init.x_type === xactInitWriteUncached)
+  }
+  def messageHasData (reply: TransactionReply): Bool = {
+    (reply.x_type != xactReplyWriteUncached && reply.x_type != xactReplyReadExclusiveAck)
+  }
+  def messageUpdatesDataArray (reply: TransactionReply): Bool = {
+    (reply.x_type === xactReplyReadExclusive)
+  }
+
+  def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool = (addr1 === addr2)
+
+  def getTransactionReplyType(x_type: UFix, count: UFix): Bits = {
+    MuxLookup(x_type, xactReplyReadUncached, Array(
+      xactInitReadExclusiveClean -> xactReplyReadExclusive,
+      xactInitReadExclusiveDirty -> xactReplyReadExclusive,
+      xactInitReadUncached  -> xactReplyReadUncached,
+      xactInitWriteUncached -> xactReplyWriteUncached
+    ))
+  }
+
+  def getProbeRequestType(x_type: UFix, global_state: UFix): UFix = {
+    MuxLookup(x_type, probeReqCopy, Array(
+      xactInitReadExclusiveClean -> probeReqInvalidate,
+      xactInitReadExclusiveDirty -> probeReqInvalidate, 
+      xactInitReadUncached -> probeReqCopy, 
+      xactInitWriteUncached -> probeReqInvalidate
+    ))
+  }
+
+  def needsMemRead(x_type: UFix, global_state: UFix): Bool = {
+      (x_type != xactInitWriteUncached)
+  }
+  def needsMemWrite(x_type: UFix, global_state: UFix): Bool = {
+      (x_type === xactInitWriteUncached)
+  }
+  def needsAckReply(x_type: UFix, global_state: UFix): Bool = {
+      (x_type === xactInitWriteUncached)
+  }
+}
+
+class FourStateCoherence extends CoherencePolicyWithUncached {
 
   val tileInvalid :: tileShared :: tileExclusiveClean :: tileExclusiveDirty :: Nil = Enum(4){ UFix() }
   val globalInvalid :: globalShared :: globalExclusiveClean :: Nil = Enum(3){ UFix() }
@@ -208,6 +461,8 @@ trait FourStateCoherence extends CoherencePolicy {
     ))
   }
 
+  def getTransactionInitTypeOnUncachedRead() = xactInitReadUncached 
+  def getTransactionInitTypeOnUncachedWrite() = xactInitWriteUncached 
   def getTransactionInitTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = {
     val (read, write) = cpuCmdToRW(cmd)
     Mux(write || cmd === M_PFW, xactInitReadExclusive, xactInitReadShared)
@@ -236,17 +491,20 @@ trait FourStateCoherence extends CoherencePolicy {
     reply
   }
 
-  def hasData (reply: ProbeReply): Bool = {
+  def messageHasData (reply: ProbeReply): Bool = {
     (reply.p_type === probeRepInvalidateData ||
      reply.p_type === probeRepDowngradeData ||
      reply.p_type === probeRepCopyData)
   }
-  def hasData (init: TransactionInit): Bool = {
+  def messageHasData (init: TransactionInit): Bool = {
     (init.x_type === xactInitWriteUncached)
   }
-  def hasData (reply: TransactionReply): Bool = {
+  def messageHasData (reply: TransactionReply): Bool = {
     (reply.x_type != xactReplyWriteUncached && reply.x_type != xactReplyReadExclusiveAck)
   }
+  def messageUpdatesDataArray (reply: TransactionReply): Bool = {
+    (reply.x_type === xactReplyReadShared || reply.x_type === xactReplyReadExclusive)
+  }
 
   def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool = (addr1 === addr2)
 

rocket/src/main/scala/htif.scala

@@ -30,7 +30,7 @@ class ioHTIF extends Bundle
   val pcr_rep = (new ioPipe) { Bits(width = 64) }
 }
 
-class rocketHTIF(w: Int, ncores: Int) extends Component with FourStateCoherence
+class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends Component
 {
   val io = new Bundle {
     val host = new ioHost(w)
@@ -165,7 +165,7 @@ class rocketHTIF(w: Int, ncores: Int) extends Component with FourStateCoherence
     mem_req_data = Cat(packet_ram(idx), mem_req_data)
   }
   io.mem.xact_init.valid := state === state_mem_req
-  io.mem.xact_init.bits.x_type := Mux(cmd === cmd_writemem, xactInitWriteUncached, xactInitReadUncached)
+  io.mem.xact_init.bits.x_type := Mux(cmd === cmd_writemem, co.getTransactionInitTypeOnUncachedWrite, co.getTransactionInitTypeOnUncachedRead)
   io.mem.xact_init.bits.address := addr >> UFix(OFFSET_BITS-3)
   io.mem.xact_init_data.valid:= state === state_mem_wdata
   io.mem.xact_init_data.bits.data := mem_req_data
@@ -175,7 +175,7 @@ class rocketHTIF(w: Int, ncores: Int) extends Component with FourStateCoherence
   val probe_q = (new queue(1)) { new ProbeReply }
   probe_q.io.enq.valid := io.mem.probe_req.valid
   io.mem.probe_req.ready := probe_q.io.enq.ready
-  probe_q.io.enq.bits := newProbeReply(io.mem.probe_req.bits, newStateOnFlush())
+  probe_q.io.enq.bits := co.newProbeReply(io.mem.probe_req.bits, co.newStateOnFlush())
   io.mem.probe_rep <> probe_q.io.deq
   io.mem.probe_rep_data.valid := Bool(false)
 

rocket/src/main/scala/icache.scala

@@ -27,7 +27,7 @@ class ioRocketICache extends Bundle()
 // 32 bit wide cpu port, 128 bit wide memory port, 64 byte cachelines
 // parameters :
 //    lines = # cache lines
-class rocketICache(sets: Int, assoc: Int) extends Component with FourStateCoherence
+class rocketICache(sets: Int, assoc: Int, co: CoherencePolicyWithUncached) extends Component
 {
   val io = new ioRocketICache();
 
@@ -136,7 +136,7 @@ class rocketICache(sets: Int, assoc: Int) extends Component with FourStateCohere
   rdy := !io.cpu.itlb_miss && (state === s_ready) && (!r_cpu_req_val || tag_hit);
   io.cpu.resp_data := data_mux.io.out
   io.mem.xact_init.valid := (state === s_request) && finish_q.io.enq.ready
-  io.mem.xact_init.bits.x_type := xactInitReadUncached
+  io.mem.xact_init.bits.x_type := co.getTransactionInitTypeOnUncachedRead
   io.mem.xact_init.bits.address := r_cpu_miss_addr(tagmsb,indexlsb).toUFix
   io.mem.xact_finish <> finish_q.io.deq
 

rocket/src/main/scala/icache_prefetch.scala

@@ -11,7 +11,7 @@ class ioIPrefetcher extends Bundle() {
   val invalidate = Bool(INPUT)
 }
 
-class rocketIPrefetcher extends Component with FourStateCoherence
+class rocketIPrefetcher(co: CoherencePolicyWithUncached) extends Component
 {
   val io = new ioIPrefetcher();
   val pdq = (new queue(REFILL_CYCLES, flushable = true)) { Bits(width = MEM_DATA_BITS) };
@@ -34,7 +34,7 @@ class rocketIPrefetcher extends Component with FourStateCoherence
   val finish_q = (new queue(1)) { new TransactionFinish }
   io.mem.xact_abort.ready := Bool(true)
   io.mem.xact_init.valid  := prefetch_miss || (state === s_req_wait) && finish_q.io.enq.ready
-  io.mem.xact_init.bits.x_type := xactInitReadUncached
+  io.mem.xact_init.bits.x_type := co.getTransactionInitTypeOnUncachedRead
   io.mem.xact_init.bits.tile_xact_id  := Mux(prefetch_miss, UFix(0), UFix(1))
   io.mem.xact_init.bits.address := Mux(prefetch_miss, io.icache.xact_init.bits.address, prefetch_addr);
 

rocket/src/main/scala/nbdcache.scala

@@ -158,7 +158,7 @@ class MetaArrayReq extends Bundle {
   val data = new MetaData()
 }
 
-class MSHR(id: Int) extends Component with FourStateCoherence {
+class MSHR(id: Int, co: CoherencePolicy) extends Component {
   val io = new Bundle {
     val req_pri_val    = Bool(INPUT)
     val req_pri_rdy    = Bool(OUTPUT)
@@ -196,7 +196,7 @@ class MSHR(id: Int) extends Component with FourStateCoherence {
   val req_cmd = io.req_bits.cmd
   val req_use_rpq = (req_cmd != M_PFR) && (req_cmd != M_PFW) && (req_cmd != M_FLA)
   val idx_match = req.idx === io.req_bits.idx
-  val sec_rdy = idx_match && !flush && (state === s_wb_req || state === s_wb_resp || (state === s_refill_req || state === s_refill_resp) && !needsTransactionOnSecondaryMiss(req_cmd, io.mem_req.bits))
+  val sec_rdy = idx_match && !flush && (state === s_wb_req || state === s_wb_resp || (state === s_refill_req || state === s_refill_resp) && !co.needsTransactionOnSecondaryMiss(req_cmd, io.mem_req.bits))
 
   val rpq = (new queue(NRPQ)) { new RPQEntry }
   rpq.io.enq.valid := (io.req_pri_val && io.req_pri_rdy || io.req_sec_val && sec_rdy) && req_use_rpq
@@ -220,7 +220,7 @@ class MSHR(id: Int) extends Component with FourStateCoherence {
     when (refill_done) { state := s_drain_rpq }
     when (reply) {
       refill_count := refill_count + UFix(1)
-      line_state := newStateOnTransactionReply(io.mem_rep.bits, io.mem_req.bits)
+      line_state := co.newStateOnTransactionReply(io.mem_rep.bits, io.mem_req.bits)
     }
     when (abort) { state := s_refill_req }
   }
@@ -239,13 +239,13 @@ class MSHR(id: Int) extends Component with FourStateCoherence {
   }
 
   when (io.req_sec_val && io.req_sec_rdy) { // s_wb_req, s_wb_resp, s_refill_req
-    xacx_type := getTransactionInitTypeOnSecondaryMiss(req_cmd, newStateOnFlush(), io.mem_req.bits)
+    xacx_type := co.getTransactionInitTypeOnSecondaryMiss(req_cmd, co.newStateOnFlush(), io.mem_req.bits)
   }
   when ((state === s_invalid) && io.req_pri_val) {
     flush := req_cmd === M_FLA
-    line_state := newStateOnFlush()
+    line_state := co.newStateOnFlush()
     refill_count := UFix(0)
-    xacx_type := getTransactionInitTypeOnPrimaryMiss(req_cmd, newStateOnFlush())
+    xacx_type := co.getTransactionInitTypeOnPrimaryMiss(req_cmd, co.newStateOnFlush())
     req := io.req_bits
 
     when (io.req_bits.tag_miss) {
@@ -289,7 +289,7 @@ class MSHR(id: Int) extends Component with FourStateCoherence {
   io.replay.bits.way_oh := req.way_oh
 }
 
-class MSHRFile extends Component {
+class MSHRFile(co: CoherencePolicy) extends Component {
   val io = new Bundle {
     val req = (new ioDecoupled) { new MSHRReq }.flip
     val secondary_miss = Bool(OUTPUT)
@@ -343,7 +343,7 @@ class MSHRFile extends Component {
   var refill_probe_rdy = Bool(true)
 
   for (i <- 0 to NMSHR-1) {
-    val mshr = new MSHR(i)
+    val mshr = new MSHR(i, co)
 
     tag_mux.io.sel(i) := mshr.io.idx_match
     tag_mux.io.in(i) := mshr.io.tag
@@ -409,7 +409,8 @@ class MSHRFile extends Component {
   io.cpu_resp_tag := Reg(replay.bits.cpu_tag)
 }
 
-class WritebackUnit extends Component with FourStateCoherence{
+
+class WritebackUnit(co: CoherencePolicy) extends Component {
   val io = new Bundle {
     val req = (new ioDecoupled) { new WritebackReq() }.flip
     val probe = (new ioDecoupled) { new WritebackReq() }.flip
@@ -469,7 +470,7 @@ class WritebackUnit extends Component with FourStateCoherence{
   io.data_req.bits.data := Bits(0)
 
   io.mem_req.valid := valid && !cmd_sent
-  io.mem_req.bits.x_type := getTransactionInitTypeOnWriteback()
+  io.mem_req.bits.x_type := co.getTransactionInitTypeOnWriteback()
   io.mem_req.bits.address := Cat(req.tag, req.idx).toUFix
   io.mem_req.bits.tile_xact_id := req.tile_xact_id
   io.mem_req_data.valid := data_req_fired && !is_probe
@@ -478,7 +479,7 @@ class WritebackUnit extends Component with FourStateCoherence{
   io.probe_rep_data.bits.data := io.data_resp
 }
 
-class ProbeUnit extends Component with FourStateCoherence {
+class ProbeUnit(co: CoherencePolicy) extends Component {
   val io = new Bundle {
     val req = (new ioDecoupled) { new ProbeRequest }.flip
     val rep = (new ioDecoupled) { new ProbeReply }
@@ -504,7 +505,7 @@ class ProbeUnit extends Component with FourStateCoherence {
     state := s_writeback_resp
   }
   when ((state === s_probe_rep) && io.meta_req.ready && io.rep.ready) {
-    state := Mux(hit && needsWriteback(line_state), s_writeback_req, s_invalid)
+    state := Mux(hit && co.needsWriteback(line_state), s_writeback_req, s_invalid)
   }
   when (state === s_meta_resp) {
     way_oh := io.tag_match_way_oh
@@ -521,13 +522,13 @@ class ProbeUnit extends Component with FourStateCoherence {
 
   io.req.ready := state === s_invalid
   io.rep.valid := state === s_probe_rep && io.meta_req.ready
-  io.rep.bits := newProbeReply(req, Mux(hit, line_state, newStateOnFlush()))
+  io.rep.bits := co.newProbeReply(req, Mux(hit, line_state, co.newStateOnFlush()))
 
   io.meta_req.valid := state === s_meta_req || state === s_meta_resp || state === s_probe_rep && hit
   io.meta_req.bits.way_en := Mux(state === s_probe_rep, way_oh, ~UFix(0, NWAYS))
   io.meta_req.bits.rw := state === s_probe_rep
   io.meta_req.bits.idx := req.address
-  io.meta_req.bits.data.state := newStateOnProbeRequest(req, line_state)
+  io.meta_req.bits.data.state := co.newStateOnProbeRequest(req, line_state)
   io.meta_req.bits.data.tag := req.address >> UFix(IDX_BITS)
   io.mshr_req.valid := state === s_meta_resp
   io.address := req.address
@@ -538,7 +539,7 @@ class ProbeUnit extends Component with FourStateCoherence {
   io.wb_req.bits.tag := req.address >> UFix(IDX_BITS)
 }
 
-class FlushUnit(lines: Int) extends Component with FourStateCoherence{
+class FlushUnit(lines: Int, co: CoherencePolicy) extends Component {
   val io = new Bundle {
     val req = (new ioDecoupled) { Bool() }.flip
     val meta_req = (new ioDecoupled) { new MetaArrayReq() }
@@ -583,7 +584,7 @@ class FlushUnit(lines: Int) extends Component with FourStateCoherence{
   io.meta_req.bits.way_en := UFixToOH(way_cnt, NWAYS)
   io.meta_req.bits.idx := idx_cnt
   io.meta_req.bits.rw := (state === s_reset)
-  io.meta_req.bits.data.state := newStateOnFlush()
+  io.meta_req.bits.data.state := co.newStateOnFlush()
   io.meta_req.bits.data.tag := UFix(0)
 }
 
@@ -732,16 +733,7 @@ class ioDmem(view: List[String] = null) extends Bundle(view) {
   val resp_tag  = Bits(DCACHE_TAG_BITS, OUTPUT);
 }
  
-abstract class HellaCache extends Component {
-  def isHit ( cmd: Bits, state: UFix): Bool
-  def isValid (state: UFix): Bool
-  def needsWriteback (state: UFix): Bool
-  def newStateOnWriteback(): UFix
-  def newStateOnFlush(): UFix
-  def newStateOnHit(cmd: Bits, state: UFix): UFix
-}
-
-class HellaCacheUniproc extends HellaCache with FourStateCoherence {
+class HellaCache(co: CoherencePolicy) extends Component {
   val io = new Bundle {
     val cpu = new ioDmem()
     val mem = new ioTileLink
@@ -794,10 +786,10 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
   val r_req_readwrite = r_req_read || r_req_write || r_req_prefetch
   val nack_hit = Wire() { Bool() }
 
-  val wb = new WritebackUnit
-  val prober = new ProbeUnit
-  val mshr = new MSHRFile()
-  val flusher = new FlushUnit(lines)
+  val wb = new WritebackUnit(co)
+  val prober = new ProbeUnit(co)
+  val mshr = new MSHRFile(co)
+  val flusher = new FlushUnit(lines, co)
   val replay_amo_val = mshr.io.data_req.valid && mshr.io.data_req.bits.cmd(3).toBool
 
   // reset and flush unit
@@ -856,10 +848,10 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
   val early_tag_nack = !meta_arb.io.in(3).ready
   val cpu_req_ppn = Mux(prober.io.mshr_req.valid, prober.io.address >> UFix(PGIDX_BITS-OFFSET_BITS), io.cpu.req_ppn)
   val cpu_req_tag = Cat(cpu_req_ppn, r_cpu_req_idx)(tagmsb,taglsb)
-  val tag_match_arr = (0 until NWAYS).map( w => isValid(meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag))
+  val tag_match_arr = (0 until NWAYS).map( w => co.isValid(meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag))
   val tag_match = Cat(Bits(0),tag_match_arr:_*).orR
   val tag_match_way_oh = Cat(Bits(0),tag_match_arr.reverse:_*)(NWAYS-1, 0) //TODO: use Vec
-  val tag_hit_arr = (0 until NWAYS).map( w => isHit(r_cpu_req_cmd, meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag))
+  val tag_hit_arr = (0 until NWAYS).map( w => co.isHit(r_cpu_req_cmd, meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag))
   val tag_hit = Cat(Bits(0),tag_hit_arr:_*).orR
   val meta_resp_way_oh = Mux(meta.io.way_en === ~UFix(0, NWAYS), tag_match_way_oh, meta.io.way_en)
   val data_resp_way_oh = Mux(data.io.way_en === ~UFix(0, NWAYS), tag_match_way_oh, data.io.way_en)
@@ -894,7 +886,7 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
   data_arb.io.in(0).bits.wmask := ~UFix(0, MEM_DATA_BITS/8)
   data_arb.io.in(0).bits.data := io.mem.xact_rep.bits.data
   data_arb.io.in(0).bits.way_en := mshr.io.mem_resp_way_oh
-  data_arb.io.in(0).valid := io.mem.xact_rep.valid && (io.mem.xact_rep.bits.x_type === xactReplyReadShared || io.mem.xact_rep.bits.x_type === xactReplyReadExclusive)
+  data_arb.io.in(0).valid := io.mem.xact_rep.valid && co.messageUpdatesDataArray(io.mem.xact_rep.bits)
 
   // load hits
   data_arb.io.in(4).bits.offset := io.cpu.req_idx(offsetmsb,ramindexlsb)
@@ -924,7 +916,7 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
   p_store_valid := p_store_valid && !drain_store || (r_cpu_req_val && tag_hit && r_req_store && mshr.io.req.ready && !nack_hit) || p_amo
 
   // tag update after a store to an exclusive clean line.
-  val new_hit_state = newStateOnHit(r_cpu_req_cmd, meta_resp_mux.state)
+  val new_hit_state = co.newStateOnHit(r_cpu_req_cmd, meta_resp_mux.state)
   val set_hit_state  = r_cpu_req_val && tag_hit && meta_resp_mux.state != new_hit_state
   meta.io.state_req.bits.rw := Bool(true)
   meta.io.state_req.bits.idx := Reg(r_cpu_req_idx(indexmsb,indexlsb))
@@ -948,7 +940,7 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
   // miss handling
   mshr.io.req.valid := r_cpu_req_val && r_req_readwrite && !nack_hit || flusher.io.mshr_req.valid
   mshr.io.req.bits.tag_miss := !tag_hit || flusher.io.mshr_req.valid
-  mshr.io.req.bits.old_dirty := needsWriteback(meta_wb_mux.state) && (!tag_match || flusher.io.mshr_req.valid) // don't wb upgrades
+  mshr.io.req.bits.old_dirty := co.needsWriteback(meta_wb_mux.state) && (!tag_match || flusher.io.mshr_req.valid) // don't wb upgrades
   mshr.io.req.bits.old_tag := meta_wb_mux.tag
   mshr.io.req.bits.tag := cpu_req_tag
   mshr.io.req.bits.idx := r_cpu_req_idx(indexmsb,indexlsb)

rocket/src/main/scala/tile.scala

@@ -4,7 +4,7 @@ import Chisel._
 import Node._
 import Constants._
 
-class Tile extends Component
+class Tile(co: CoherencePolicyWithUncached) extends Component
 {
   val io = new Bundle {
     val tilelink = new ioTileLink
@@ -12,8 +12,8 @@ class Tile extends Component
   }
   
   val cpu       = new rocketProc(resetSignal = io.host.reset)
-  val icache    = new rocketICache(128, 4) // 128 sets x 4 ways (32KB)
-  val dcache    = new HellaCacheUniproc
+  val icache    = new rocketICache(128, 4, co) // 128 sets x 4 ways (32KB)
+  val dcache    = new HellaCache(co)
 
   val arbiter   = new rocketMemArbiter(2 + (if (HAVE_VEC) 1 else 0))
   arbiter.io.requestor(0) <> dcache.io.mem
@@ -30,7 +30,7 @@ class Tile extends Component
 
   if (HAVE_VEC)
   {
-    val vicache = new rocketICache(128, 1) // 128 sets x 1 ways (8KB)
+    val vicache = new rocketICache(128, 1, co) // 128 sets x 1 ways (8KB)
     arbiter.io.requestor(2) <> vicache.io.mem
     cpu.io.vimem <> vicache.io.cpu
   }

rocket/src/main/scala/top.scala

@@ -20,10 +20,11 @@ class Top extends Component
   val htif_width = 8
   val io = new ioTop(htif_width)
 
-  val tile = new Tile
-  val htif = new rocketHTIF(htif_width, 1)
+  val co = new FourStateCoherence
+  val tile = new Tile(co)
+  val htif = new rocketHTIF(htif_width, 1, co)
   
-  val hub = new CoherenceHubBroadcast(2)
+  val hub = new CoherenceHubBroadcast(2, co)
   hub.io.tiles(0) <> tile.io.tilelink
   hub.io.tiles(1) <> htif.io.mem
 

rocket/src/main/scala/uncore.scala

@@ -50,7 +50,7 @@ class ioTileLink extends Bundle {
   val xact_finish    = (new ioDecoupled) { new TransactionFinish }
 }
 
-class XactTracker(ntiles: Int, id: Int) extends Component with FourStateCoherence {
+class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component {
   val io = new Bundle {
     val alloc_req       = (new ioDecoupled) { new TrackerAllocReq }.flip
     val p_data          = (new ioPipe) { new TrackerProbeData }.flip
@@ -140,7 +140,7 @@ class XactTracker(ntiles: Int, id: Int) extends Component with FourStateCoherenc
   io.sharer_count := UFix(ntiles) // TODO: Broadcast only
   io.x_type := x_type_
 
-  io.mem_req_cmd.valid              := Bool(false)
+  io.mem_req_cmd.valid := Bool(false)
   io.mem_req_cmd.bits.rw := Bool(false)
   io.mem_req_cmd.bits.addr := addr_
   io.mem_req_cmd.bits.tag := UFix(id)
@@ -148,7 +148,7 @@ class XactTracker(ntiles: Int, id: Int) extends Component with FourStateCoherenc
   io.mem_req_data.bits.data := UFix(0)
   io.mem_req_lock := Bool(false)
   io.probe_req.valid := Bool(false)
-  io.probe_req.bits.p_type := getProbeRequestType(x_type_, UFix(0))
+  io.probe_req.bits.p_type := co.getProbeRequestType(x_type_, UFix(0))
   io.probe_req.bits.global_xact_id  := UFix(id)
   io.probe_req.bits.address := addr_
   io.push_p_req      := Bits(0, width = ntiles)
@@ -167,8 +167,8 @@ class XactTracker(ntiles: Int, id: Int) extends Component with FourStateCoherenc
         x_type_ := io.alloc_req.bits.xact_init.x_type
         init_tile_id_ := io.alloc_req.bits.tile_id
         tile_xact_id_ := io.alloc_req.bits.xact_init.tile_xact_id
-        x_init_data_needs_write := hasData(io.alloc_req.bits.xact_init)
-        x_needs_read := needsMemRead(io.alloc_req.bits.xact_init.x_type, UFix(0))
+        x_init_data_needs_write := co.messageHasData(io.alloc_req.bits.xact_init)
+        x_needs_read := co.needsMemRead(io.alloc_req.bits.xact_init.x_type, UFix(0))
         if(ntiles > 1) p_rep_count := UFix(ntiles-1)
         val p_req_initial_flags = ~( UFix(1) << io.alloc_req.bits.tile_id ) //TODO: Broadcast only
         p_req_flags := p_req_initial_flags
@@ -226,7 +226,7 @@ class XactTracker(ntiles: Int, id: Int) extends Component with FourStateCoherenc
       } . elsewhen (x_needs_read) {    
         doMemReqRead(io.mem_req_cmd, x_needs_read)
       } . otherwise { 
-        state := Mux(needsAckReply(x_type_, UFix(0)), s_ack, s_busy)
+        state := Mux(co.needsAckReply(x_type_, UFix(0)), s_ack, s_busy)
       }
     }
     is(s_ack) {
@@ -241,17 +241,17 @@ class XactTracker(ntiles: Int, id: Int) extends Component with FourStateCoherenc
   }
 }
 
-abstract class CoherenceHub(ntiles: Int) extends Component with CoherencePolicy {
+abstract class CoherenceHub(ntiles: Int, co: CoherencePolicy) extends Component {
   val io = new Bundle {
     val tiles = Vec(ntiles) { new ioTileLink() }.flip
     val mem = new ioMem
   }
 }
 
-class CoherenceHubNull extends CoherenceHub(1) with ThreeStateIncoherence 
+class CoherenceHubNull(co: ThreeStateIncoherence)  extends CoherenceHub(1, co)
 {
   val x_init = io.tiles(0).xact_init
-  val is_write = x_init.bits.x_type === xactInitWriteback
+  val is_write = x_init.bits.x_type === co.xactInitWriteback
   x_init.ready := io.mem.req_cmd.ready && !(is_write && io.mem.resp.valid) //stall write req/resp to handle previous read resp
   io.mem.req_cmd.valid   := x_init.valid && !(is_write && io.mem.resp.valid)
   io.mem.req_cmd.bits.rw    := is_write
@@ -260,7 +260,7 @@ class CoherenceHubNull extends CoherenceHub(1) with ThreeStateIncoherence
   io.mem.req_data <> io.tiles(0).xact_init_data
 
   val x_rep = io.tiles(0).xact_rep
-  x_rep.bits.x_type := Mux(io.mem.resp.valid, xactReplyData, xactReplyAck)
+  x_rep.bits.x_type := Mux(io.mem.resp.valid, co.xactReplyData, co.xactReplyAck)
   x_rep.bits.tile_xact_id := Mux(io.mem.resp.valid, io.mem.resp.bits.tag, x_init.bits.tile_xact_id)
   x_rep.bits.global_xact_id := UFix(0) // don't care
   x_rep.bits.data := io.mem.resp.bits.data
@@ -275,9 +275,9 @@ class CoherenceHubNull extends CoherenceHub(1) with ThreeStateIncoherence
 }
 
 
-class CoherenceHubBroadcast(ntiles: Int) extends CoherenceHub(ntiles) with FourStateCoherence
+class CoherenceHubBroadcast(ntiles: Int, co: CoherencePolicy) extends CoherenceHub(ntiles, co)
 {
-  val trackerList = (0 until NGLOBAL_XACTS).map(new XactTracker(ntiles, _))
+  val trackerList = (0 until NGLOBAL_XACTS).map(new XactTracker(ntiles, _, co))
 
   val busy_arr           = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }
   val addr_arr           = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=PADDR_BITS-OFFSET_BITS)} }
@@ -344,12 +344,12 @@ class CoherenceHubBroadcast(ntiles: Int) extends CoherenceHub(ntiles) with FourS
     rep.bits.require_ack := Bool(true)
     rep.valid := Bool(false)
     when(io.mem.resp.valid && (UFix(j) === init_tile_id_arr(mem_idx))) {
-      rep.bits.x_type := getTransactionReplyType(x_type_arr(mem_idx), sh_count_arr(mem_idx))
+      rep.bits.x_type := co.getTransactionReplyType(x_type_arr(mem_idx), sh_count_arr(mem_idx))
       rep.bits.tile_xact_id := tile_xact_id_arr(mem_idx)
       rep.bits.global_xact_id := mem_idx
       rep.valid := Bool(true)
     } . otherwise {
-      rep.bits.x_type := getTransactionReplyType(x_type_arr(ack_idx), sh_count_arr(ack_idx))
+      rep.bits.x_type := co.getTransactionReplyType(x_type_arr(ack_idx), sh_count_arr(ack_idx))
       rep.bits.tile_xact_id := tile_xact_id_arr(ack_idx)
       rep.bits.global_xact_id := ack_idx
       when (UFix(j) === init_tile_id_arr(ack_idx)) {
@@ -417,16 +417,16 @@ class CoherenceHubBroadcast(ntiles: Int) extends CoherenceHub(ntiles) with FourS
     val conflicts = Vec(NGLOBAL_XACTS) { Wire() { Bool() } }
     for( i <- 0 until NGLOBAL_XACTS) {
       val t = trackerList(i).io
-      conflicts(i) := t.busy && x_init.valid && isCoherenceConflict(t.addr, x_init.bits.address)
+      conflicts(i) := t.busy && x_init.valid && co.isCoherenceConflict(t.addr, x_init.bits.address)
     }
     x_abort.bits.tile_xact_id := x_init.bits.tile_xact_id
-    want_to_abort_arr(j) := x_init.valid && (conflicts.toBits.orR || busy_arr.toBits.andR || (!x_init_data_dep_list(j).io.enq.ready && hasData(x_init.bits)))
+    want_to_abort_arr(j) := x_init.valid && (conflicts.toBits.orR || busy_arr.toBits.andR || (!x_init_data_dep_list(j).io.enq.ready && co.messageHasData(x_init.bits)))
     
     x_abort.valid := Bool(false)
     switch(abort_state_arr(j)) {
       is(s_idle) {
         when(want_to_abort_arr(j)) {
-          when(hasData(x_init.bits)) {
+          when(co.messageHasData(x_init.bits)) {
             abort_state_arr(j) := s_abort_drain
           } . otherwise {
             abort_state_arr(j) := s_abort_send
@@ -478,7 +478,7 @@ class CoherenceHubBroadcast(ntiles: Int) extends CoherenceHub(ntiles) with FourS
     init_arb.io.in(j).bits.tile_id := UFix(j)
     val pop_x_inits = trackerList.map(_.io.pop_x_init(j).toBool)
     val do_pop = foldR(pop_x_inits)(_||_)
-    x_init_data_dep_list(j).io.enq.valid := do_pop && hasData(x_init.bits) && (abort_state_arr(j) === s_idle) 
+    x_init_data_dep_list(j).io.enq.valid := do_pop && co.messageHasData(x_init.bits) && (abort_state_arr(j) === s_idle) 
     x_init_data_dep_list(j).io.enq.bits.global_xact_id := OHToUFix(pop_x_inits)
     x_init.ready := (abort_state_arr(j) === s_abort_complete) || do_pop
     x_init_data.ready := (abort_state_arr(j) === s_abort_drain) || foldR(trackerList.map(_.io.pop_x_init_data(j).toBool))(_||_)