riscv/rocket-chip
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rename queue to Queue

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fixes build with case-insensitive file system
This commit is contained in:
Andrew Waterman 2012-08-08 22:11:32 -07:00
parent 897a4e349b
commit 0f20771664
10 changed files with 15 additions and 111 deletions
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2
rocket/src/main/scala/htif.scala
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@ -121,7 +121,7 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
}
val mem_cnt = Reg(resetVal = UFix(0, log2Up(REFILL_CYCLES)))
val x_init = new queue(1)(new TransactionInit)
val x_init = new Queue(1)(new TransactionInit)
when (state === state_mem_req && x_init.io.enq.ready) {
state := Mux(cmd === cmd_writemem, state_mem_wdata, state_mem_rdata)
}

2
rocket/src/main/scala/icache.scala
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@ -127,7 +127,7 @@ class rocketICache(sets: Int, assoc: Int, co: CoherencePolicyWithUncached) exten
}
tag_hit := any_hit
val finish_q = (new queue(1)) { new TransactionFinish }
val finish_q = (new Queue(1)) { new TransactionFinish }
finish_q.io.enq.valid := refill_done && io.mem.xact_rep.bits.require_ack
finish_q.io.enq.bits.global_xact_id := io.mem.xact_rep.bits.global_xact_id

96
rocket/src/main/scala/icache_prefetch.scala
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@ -1,96 +0,0 @@
package rocket
import Chisel._;
import Node._;
import Constants._;
import scala.math._;
class ioIPrefetcher extends Bundle() {
val icache = new ioTileLink().flip
val mem = new ioTileLink
val invalidate = Bool(INPUT)
}
class rocketIPrefetcher(co: CoherencePolicyWithUncached) extends Component
{
val io = new ioIPrefetcher();
val pdq = (new queue(REFILL_CYCLES, flushable = true)) { Bits(width = MEM_DATA_BITS) };
val s_invalid :: s_valid :: s_refilling :: s_req_wait :: s_resp_wait :: s_bad_resp_wait :: Nil = Enum(6) { UFix() };
val state = Reg(resetVal = s_invalid);
val ip_mem_resp_abort = io.mem.xact_abort.valid && io.mem.xact_abort.bits.tile_xact_id(0)
val demand_miss = io.icache.xact_init.valid && io.icache.xact_init.ready
val prefetch_addr = Reg() { UFix(width = io.icache.xact_init.bits.address.width) };
val addr_match = (prefetch_addr === io.icache.xact_init.bits.address);
val hit = (state != s_invalid) && (state != s_req_wait) && addr_match && !ip_mem_resp_abort
val prefetch_miss = io.icache.xact_init.valid && !hit
when (demand_miss) { prefetch_addr := io.icache.xact_init.bits.address + UFix(1); }
io.icache.xact_init.ready := io.mem.xact_init.ready
val ip_mem_resp_val = io.mem.xact_rep.valid && io.mem.xact_rep.bits.tile_xact_id(0)
val ip_mem_req_rdy = io.mem.xact_init.ready && !prefetch_miss
val finish_q = (new queue(1)) { new TransactionFinish }
io.mem.xact_abort.ready := Bool(true)
io.mem.xact_init.valid := prefetch_miss || (state === s_req_wait) && finish_q.io.enq.ready
io.mem.xact_init.bits.x_type := co.getTransactionInitTypeOnUncachedRead
io.mem.xact_init.bits.tile_xact_id := Mux(prefetch_miss, UFix(0), UFix(1))
io.mem.xact_init.bits.address := Mux(prefetch_miss, io.icache.xact_init.bits.address, prefetch_addr);
val finish_arb = (new Arbiter(2)) { new TransactionFinish }
finish_arb.io.in(0) <> io.icache.xact_finish
finish_arb.io.in(1) <> finish_q.io.deq
io.mem.xact_finish <> finish_arb.io.out
val fill_cnt = Reg(resetVal = UFix(0, log2Up(REFILL_CYCLES)))
when (ip_mem_resp_val) { fill_cnt := fill_cnt + UFix(1) }
val fill_done = fill_cnt.andR && ip_mem_resp_val
finish_q.io.enq.valid := fill_done && io.mem.xact_rep.bits.require_ack
finish_q.io.enq.bits.global_xact_id := io.mem.xact_rep.bits.global_xact_id
val forward = Reg(resetVal = Bool(false))
val forward_cnt = Reg(resetVal = UFix(0, log2Up(REFILL_CYCLES)))
when (forward && pdq.io.deq.valid) { forward_cnt := forward_cnt + UFix(1) }
val forward_done = forward_cnt.andR && pdq.io.deq.valid
forward := demand_miss && hit || forward && !forward_done
io.icache.xact_abort.valid := io.mem.xact_abort.valid && !io.mem.xact_abort.bits.tile_xact_id(0) ||
forward && ip_mem_resp_abort
io.icache.xact_rep.valid := io.mem.xact_rep.valid && !io.mem.xact_rep.bits.tile_xact_id(0) || (forward && pdq.io.deq.valid)
io.icache.xact_rep.bits.data := Mux(forward, pdq.io.deq.bits, io.mem.xact_rep.bits.data)
io.icache.xact_rep.bits.require_ack := !forward && io.mem.xact_rep.bits.require_ack
io.icache.xact_rep.bits.global_xact_id := io.mem.xact_rep.bits.global_xact_id
pdq.io.flush := Reg(demand_miss && !hit || (state === s_bad_resp_wait), resetVal = Bool(false))
pdq.io.enq.bits := io.mem.xact_rep.bits.data
pdq.io.enq.valid := ip_mem_resp_val
pdq.io.deq.ready := forward
switch (state) {
is (s_invalid) {
when (demand_miss) { state := s_req_wait; }
}
is (s_valid) {
when (demand_miss || forward && forward_done) { state := s_req_wait }
.elsewhen (io.invalidate && !forward) { state := s_invalid }
}
is (s_refilling) {
when (demand_miss && !addr_match && fill_done) { state := s_req_wait }
.elsewhen (fill_done) { state := Mux(io.invalidate, s_invalid, s_valid) }
.elsewhen (demand_miss && !addr_match || io.invalidate) { state := s_bad_resp_wait }
}
is (s_req_wait) {
when (ip_mem_req_rdy && finish_q.io.enq.ready) { state := s_resp_wait }
}
is (s_resp_wait) {
when (ip_mem_resp_abort) { state := s_invalid }
.elsewhen (demand_miss && !addr_match || io.invalidate) { state := s_bad_resp_wait }
.elsewhen (ip_mem_resp_val) { state := s_refilling }
}
is (s_bad_resp_wait) {
when (fill_done || ip_mem_resp_abort) { state := s_req_wait }
}
}
}

2
rocket/src/main/scala/llc.scala
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@ -245,7 +245,7 @@ class LLCData(latency: Int, sets: Int, ways: Int, leaf: Mem[Bits]) extends Compo
val isWriteback = Bool()
override def clone = new QEntry().asInstanceOf[this.type]
}
val q = (new queue(latency+2)) { new QEntry }
val q = (new Queue(latency+2)) { new QEntry }
val qReady = q.io.count <= UFix(q.entries-latency-1)
val valid = Reg(resetVal = Bool(false))
val req = Reg() { io.req.bits.clone }

2
rocket/src/main/scala/memserdes.scala
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@ -149,7 +149,7 @@ class MemDessert extends Component // test rig side
io.wide.req_data.valid := state === s_data
io.wide.req_data.bits.data := in_buf >> UFix(((rbits+MEM_BACKUP_WIDTH-1)/MEM_BACKUP_WIDTH - (dbits+MEM_BACKUP_WIDTH-1)/MEM_BACKUP_WIDTH)*MEM_BACKUP_WIDTH)
val dataq = (new queue(REFILL_CYCLES)) { new MemResp }
val dataq = (new Queue(REFILL_CYCLES)) { new MemResp }
dataq.io.enq <> io.wide.resp
dataq.io.deq.ready := recv_cnt === UFix((rbits-1)/MEM_BACKUP_WIDTH)

2
rocket/src/main/scala/multiplier.scala
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@ -48,7 +48,7 @@ class rocketVUMultiplier(nwbq: Int) extends Component {
inflight_cnt = inflight_cnt + wbq_cnt
val wbq_rdy = inflight_cnt < UFix(nwbq)
val wbq = (new queue(nwbq)) { Bits(width = io.cpu.resp_bits.width + io.cpu.resp_tag.width) }
val wbq = (new Queue(nwbq)) { Bits(width = io.cpu.resp_bits.width + io.cpu.resp_tag.width) }
wbq.io.enq.valid := valid(0)
wbq.io.enq.bits := Cat(io.vu.resp, tag(0))
wbq.io.deq.ready := io.cpu.resp_rdy

4
rocket/src/main/scala/nbdcache.scala
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@ -198,7 +198,7 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component {
val idx_match = req.idx === io.req_bits.idx
val sec_rdy = idx_match && !flush && (state === s_wb_req || state === s_wb_resp || state === s_meta_clear || (state === s_refill_req || state === s_refill_resp) && !co.needsTransactionOnSecondaryMiss(req_cmd, io.mem_req.bits))
val rpq = (new queue(NRPQ)) { new RPQEntry }
val rpq = (new Queue(NRPQ)) { new RPQEntry }
rpq.io.enq.valid := (io.req_pri_val && io.req_pri_rdy || io.req_sec_val && sec_rdy) && req_use_rpq
rpq.io.enq.bits := io.req_bits
rpq.io.enq.bits.sdq_id := io.req_sdq_id
@ -209,7 +209,7 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component {
val refill_done = reply && refill_count.andR
val wb_done = reply && (state === s_wb_resp)
val finish_q = (new queue(2 /* wb + refill */)) { new TransactionFinish }
val finish_q = (new Queue(2 /* wb + refill */)) { new TransactionFinish }
finish_q.io.enq.valid := wb_done || refill_done
finish_q.io.enq.bits.global_xact_id := io.mem_rep.bits.global_xact_id

8
rocket/src/main/scala/queues.scala
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@ -11,7 +11,7 @@ class ioQueue[T <: Data](entries: Int, flushable: Boolean)(data: => T) extends B
val count = UFix(OUTPUT, log2Up(entries+1))
}
class queue[T <: Data](val entries: Int, pipe: Boolean = false, flow: Boolean = false, flushable: Boolean = false)(data: => T) extends Component
class Queue[T <: Data](val entries: Int, pipe: Boolean = false, flow: Boolean = false, flushable: Boolean = false)(data: => T) extends Component
{
val io = new ioQueue(entries, flushable)(data)
@ -66,7 +66,7 @@ class queue[T <: Data](val entries: Int, pipe: Boolean = false, flow: Boolean =
object Queue
{
def apply[T <: Data](enq: FIFOIO[T], entries: Int = 2, pipe: Boolean = false) = {
val q = (new queue(entries, pipe)) { enq.bits.clone }
val q = (new Queue(entries, pipe)) { enq.bits.clone }
q.io.enq.valid := enq.valid // not using <> so that override is allowed
q.io.enq.bits := enq.bits
enq.ready := q.io.enq.ready
@ -115,8 +115,8 @@ class SkidBuffer[T <: Data]()(data: => T) extends Component
val deq = new FIFOIO()(data)
}
val fq = new queue(1, flow = true)(data)
val pq = new queue(1, pipe = true)(data)
val fq = new Queue(1, flow = true)(data)
val pq = new Queue(1, pipe = true)(data)
fq.io.enq <> io.enq
pq.io.enq <> fq.io.deq

4
rocket/src/main/scala/slowio.scala
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@ -28,12 +28,12 @@ class slowIO[T <: Data](val divisor: Int, hold_cycles_in: Int = -1)(data: => T)
val out_slow_val = Reg(resetVal = Bool(false))
val out_slow_bits = Reg() { data }
val fromhost_q = new queue(1)(data)
val fromhost_q = new Queue(1)(data)
fromhost_q.io.enq.valid := in_en && (io.in_slow.valid && in_slow_rdy || reset)
fromhost_q.io.enq.bits := io.in_slow.bits
fromhost_q.io.deq <> io.in_fast
val tohost_q = new queue(1)(data)
val tohost_q = new Queue(1)(data)
tohost_q.io.enq <> io.out_fast
tohost_q.io.deq.ready := in_en && io.out_slow.ready && out_slow_val

4
rocket/src/main/scala/uncore.scala
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@ -336,8 +336,8 @@ class CoherenceHubBroadcast(ntiles: Int, co: CoherencePolicy) extends CoherenceH
}
}
val p_rep_data_dep_list = List.fill(ntiles)((new queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth must >= NPRIMARY
val x_init_data_dep_list = List.fill(ntiles)((new queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth should >= NPRIMARY
val p_rep_data_dep_list = List.fill(ntiles)((new Queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth must >= NPRIMARY
val x_init_data_dep_list = List.fill(ntiles)((new Queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth should >= NPRIMARY
// Free finished transactions
for( j <- 0 until ntiles ) {