clean up I$ parity code
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55082e45c4
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b514c7b725
@ -14,26 +14,38 @@ abstract class Decoding
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def error = correctable || uncorrectable
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}
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abstract class Encoding
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abstract class Code
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{
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def width(w0: Int): Int
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def encode(x: Bits): Bits
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def decode(x: Bits): Decoding
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}
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class Parity extends Encoding
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class IdentityCode extends Code
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{
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def width(w0: Int) = w0
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def encode(x: Bits) = x
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def decode(y: Bits) = new Decoding {
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def uncorrected = y
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def corrected = y
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def correctable = Bool(false)
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def uncorrectable = Bool(false)
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}
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}
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class ParityCode extends Code
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{
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def width(w0: Int) = w0+1
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def encode(x: Bits) = Cat(x.xorR, x)
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def decode(y: Bits) = new Decoding {
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def uncorrected = y(y.getWidth-2,0)
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def corrected = uncorrected
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def correctable = y.xorR
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def uncorrectable = Bool(false)
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def correctable = Bool(false)
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def uncorrectable = y.xorR
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}
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}
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class SEC extends Encoding
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class SECCode extends Code
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{
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def width(k: Int) = {
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val m = log2Up(k) + 1 - !isPow2(k)
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@ -75,30 +87,37 @@ class SEC extends Encoding
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private def mapping(i: Int) = i-1-log2Up(i)
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}
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class SECDED extends Encoding
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class SECDEDCode extends Code
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{
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def width(k: Int) = new SEC().width(k)+1
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def encode(x: Bits) = new Parity().encode(new SEC().encode(x))
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private val sec = new SECCode
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private val par = new ParityCode
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def width(k: Int) = sec.width(k)+1
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def encode(x: Bits) = par.encode(sec.encode(x))
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def decode(x: Bits) = new Decoding {
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val sec = new SEC().decode(x(x.getWidth-2,0))
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val par = new Parity().decode(x)
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def uncorrected = sec.uncorrected
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def corrected = sec.corrected
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def correctable = par.correctable
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def uncorrectable = !par.correctable && sec.correctable
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val secdec = sec.decode(x(x.getWidth-2,0))
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val pardec = par.decode(x)
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def uncorrected = secdec.uncorrected
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def corrected = secdec.corrected
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def correctable = pardec.uncorrectable
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def uncorrectable = !pardec.uncorrectable && secdec.correctable
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}
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}
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object ErrGen
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{
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// generate a 1-bit error with approximate probability 2^-f
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def apply(width: Int, f: Int): Bits = {
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require(width > 0 && f >= 0 && log2Up(width) + f <= 16)
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UFixToOH(LFSR16()(log2Up(width)+f-1,0))(width-1,0)
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}
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def apply(x: Bits, f: Int): Bits = x ^ apply(x.getWidth, f)
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}
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class SECDEDTest extends Component
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{
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def inject(x: Bits, n: UFix) = {
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val r = LFSR16()
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val r1 = UFixToOH(r(log2Up(x.getWidth)-1,0))(x.getWidth-1,0)
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val r2 = UFixToOH(r(log2Up(x.getWidth)*2-1,log2Up(x.getWidth)))(x.getWidth-1,0)
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x ^ Mux(n < UFix(1), UFix(0), r1) ^ Mux(n < UFix(2), UFix(0), r2)
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}
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val code = new SECDED
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val code = new SECDEDCode
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val k = 4
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val n = code.width(k)
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@ -115,7 +134,7 @@ class SECDEDTest extends Component
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val c = Counter(Bool(true), 1 << k)
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val numErrors = Counter(c._2, 3)._1
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val e = code.encode(c._1)
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val i = inject(e, numErrors)
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val i = e ^ Mux(numErrors < 1, 0, ErrGen(n, 1)) ^ Mux(numErrors < 2, 0, ErrGen(n, 1))
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val d = code.decode(i)
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io.original := c._1
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@ -7,7 +7,7 @@ import uncore._
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import Util._
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case class ICacheConfig(sets: Int, assoc: Int, co: CoherencePolicyWithUncached,
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parity: Boolean = false)
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code: Code = new IdentityCode)
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{
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val w = 1
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val ibytes = 4
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@ -15,12 +15,10 @@ case class ICacheConfig(sets: Int, assoc: Int, co: CoherencePolicyWithUncached,
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val dm = assoc == 1
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val lines = sets * assoc
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val databits = MEM_DATA_BITS
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val datawidth = databits + (if (parity) 1 else 0)
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val idxbits = log2Up(sets)
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val offbits = OFFSET_BITS
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val untagbits = idxbits + offbits
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val tagbits = PADDR_BITS - untagbits
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val tagwidth = tagbits + (if (parity) 1 else 0)
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require(isPow2(sets) && isPow2(assoc))
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require(isPow2(w) && isPow2(ibytes))
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@ -176,11 +174,12 @@ class ICache(implicit c: ICacheConfig) extends Component
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val (rf_cnt, refill_done) = Counter(io.mem.xact_rep.valid, REFILL_CYCLES)
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val repl_way = if (c.dm) UFix(0) else LFSR16(s2_miss)(log2Up(c.assoc)-1,0)
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val tag_array = Mem(c.sets, seqRead = true) { Bits(width = c.tagwidth*c.assoc) }
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val enc_tagbits = c.code.width(c.tagbits)
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val tag_array = Mem(c.sets, seqRead = true) { Bits(width = enc_tagbits*c.assoc) }
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val tag_rdata = Reg() { Bits() }
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when (refill_done) {
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val wmask = FillInterleaved(c.tagwidth, if (c.dm) Bits(1) else UFixToOH(repl_way))
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val tag = Cat(if (c.parity) s2_tag.xorR else null, s2_tag)
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val wmask = FillInterleaved(enc_tagbits, if (c.dm) Bits(1) else UFixToOH(repl_way))
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val tag = c.code.encode(s2_tag)
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tag_array.write(s2_idx, Fill(c.assoc, tag), wmask)
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}
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/*.else*/when (s0_valid) { // uncomment ".else" to infer 6T SRAM
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@ -201,39 +200,37 @@ class ICache(implicit c: ICacheConfig) extends Component
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val s1_tag_match = Vec(c.assoc) { Bool() }
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val s2_tag_hit = Vec(c.assoc) { Bool() }
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val s2_data_disparity = Vec(c.assoc) { Bool() }
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val s2_dout = Vec(c.assoc){Reg{Bits()}}
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for (i <- 0 until c.assoc) {
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val s1_vb = vb_array(Cat(UFix(i), s1_pgoff(c.untagbits-1,c.offbits))).toBool
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val s2_vb = Reg() { Bool() }
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val s2_tag_disparity = Reg() { Bool() }
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val s2_tag_match = Reg() { Bool() }
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val tag_out = tag_rdata(c.tagwidth*(i+1)-1, c.tagwidth*i)
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val tag_out = tag_rdata(enc_tagbits*(i+1)-1, enc_tagbits*i)
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when (s1_valid && rdy && !stall) {
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s2_vb := s1_vb
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s2_tag_disparity := tag_out.xorR
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s2_tag_disparity := c.code.decode(tag_out).error
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s2_tag_match := s1_tag_match(i)
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}
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s1_tag_match(i) := tag_out(c.tagbits-1,0) === s1_tag
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s2_tag_hit(i) := s2_vb && s2_tag_match
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s2_disparity(i) := Bool(c.parity) && s2_vb && (s2_tag_disparity || s2_data_disparity(i))
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s2_disparity(i) := s2_vb && (s2_tag_disparity || c.code.decode(s2_dout(i)).error)
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}
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s2_any_tag_hit := s2_tag_hit.reduceLeft(_||_) && !s2_disparity.reduceLeft(_||_)
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val s2_dout = Vec(c.assoc) { Reg() { Bits(width = c.databits) } }
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for (i <- 0 until c.assoc) {
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val data_array = Mem(c.sets*REFILL_CYCLES, seqRead = true){ Bits(width = c.datawidth) }
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val data_array = Mem(c.sets*REFILL_CYCLES, seqRead = true){ Bits(width = c.code.width(c.databits)) }
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val s1_dout = Reg(){ Bits() }
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when (io.mem.xact_rep.valid && repl_way === UFix(i)) {
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val d = io.mem.xact_rep.bits.data
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val wdata = if (c.parity) Cat(d.xorR, d) else d
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data_array(Cat(s2_idx,rf_cnt)) := wdata
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data_array(Cat(s2_idx,rf_cnt)) := c.code.encode(d)
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}
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/*.else*/when (s0_valid) { // uncomment ".else" to infer 6T SRAM
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s1_dout := data_array(s0_pgoff(c.untagbits-1,c.offbits-rf_cnt.getWidth))
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}
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// if s1_tag_match is critical, replace with partial tag check
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when (s1_valid && rdy && !stall && (Bool(c.dm) || s1_tag_match(i))) { s2_dout(i) := s1_dout }
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s2_data_disparity(i) := s2_dout(i).xorR
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}
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val s2_dout_word = s2_dout.map(x => (x >> (s2_offset(log2Up(c.databits/8)-1,log2Up(c.ibytes)) << log2Up(c.ibytes*8)))(c.ibytes*8-1,0))
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io.resp.bits.data := Mux1H(s2_tag_hit, s2_dout_word)
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