Ignore LSB of PC
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parent
59f5358435
commit
1edb1e2a0a
@ -59,7 +59,8 @@ class Frontend(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Modu
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val icache = Module(new ICache)
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val tlb = Module(new TLB(c.ntlb))
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val s1_pc = Reg(UInt())
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val s1_pc_ = Reg(UInt())
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val s1_pc = s1_pc_ & SInt(-2) // discard LSB of PC (throughout the pipeline)
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val s1_same_block = Reg(Bool())
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val s2_valid = Reg(init=Bool(true))
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val s2_pc = Reg(init=UInt(START_ADDR))
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@ -77,7 +78,7 @@ class Frontend(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Modu
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val stall = io.cpu.resp.valid && !io.cpu.resp.ready
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when (!stall) {
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s1_same_block := s0_same_block && !tlb.io.resp.miss
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s1_pc := npc
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s1_pc_ := npc
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s2_valid := !icmiss
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when (!icmiss) {
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s2_pc := s1_pc
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@ -87,7 +88,7 @@ class Frontend(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Modu
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}
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when (io.cpu.req.valid) {
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s1_same_block := Bool(false)
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s1_pc := io.cpu.req.bits.pc
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s1_pc_ := io.cpu.req.bits.pc
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s2_valid := Bool(false)
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}
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