move icache invalidate out of request bundle
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parent
6d10115b19
commit
ff8c736d94
@ -58,7 +58,7 @@ class Core(implicit conf: RocketConfiguration) extends Component
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ptw += io.vimem.ptw
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io.vimem.req.bits.pc := vu.io.imem_req.bits
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io.vimem.req.valid := vu.io.imem_req.valid
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io.vimem.req.bits.invalidate := ctrl.io.dpath.flush_inst
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io.vimem.invalidate := ctrl.io.imem.invalidate
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vu.io.imem_resp.valid := io.vimem.resp.valid
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vu.io.imem_resp.bits.pc := io.vimem.resp.bits.pc
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vu.io.imem_resp.bits.data := io.vimem.resp.bits.data
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@ -35,7 +35,6 @@ class ioCtrlDpath extends Bundle()
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val mem_wen = Bool(OUTPUT);
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val wb_wen = Bool(OUTPUT);
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val wb_valid = Bool(OUTPUT)
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val flush_inst = Bool(OUTPUT);
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val ex_mem_type = Bits(OUTPUT, 3)
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// exception handling
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val exception = Bool(OUTPUT);
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@ -391,7 +390,6 @@ class Control(implicit conf: RocketConfiguration) extends Component
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val mem_reg_cause = Reg(){UFix()}
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val mem_reg_mem_type = Reg(){Bits()}
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val wb_reg_valid = Reg(resetVal = Bool(false))
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val wb_reg_pcr = Reg(resetVal = PCR_N)
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val wb_reg_wen = Reg(resetVal = Bool(false))
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@ -407,6 +405,7 @@ class Control(implicit conf: RocketConfiguration) extends Component
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val wb_reg_div_mul_val = Reg(resetVal = Bool(false))
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val take_pc = Bool()
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val pc_taken = Reg(take_pc, resetVal = Bool(false))
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val take_pc_wb = Bool()
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val ctrl_killd = Bool()
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val ctrl_killx = Bool()
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@ -739,9 +738,8 @@ class Control(implicit conf: RocketConfiguration) extends Component
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ctrl_killd := !io.imem.resp.valid || take_pc || ctrl_stalld || id_interrupt
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io.dpath.killd := take_pc || ctrl_stalld && !id_interrupt
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io.dpath.flush_inst := wb_reg_flush_inst;
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io.imem.resp.ready := take_pc || !ctrl_stalld
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io.imem.req.bits.invalidate := wb_reg_flush_inst
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io.imem.resp.ready := pc_taken || !ctrl_stalld
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io.imem.invalidate := wb_reg_flush_inst
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io.dpath.mem_load := mem_reg_mem_val && mem_reg_wen
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io.dpath.ren2 := id_renx2.toBool;
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@ -29,7 +29,6 @@ case class ICacheConfig(sets: Int, assoc: Int, co: CoherencePolicyWithUncached,
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class FrontendReq extends Bundle {
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val pc = UFix(width = VADDR_BITS+1)
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val invalidate = Bool()
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val mispredict = Bool()
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val taken = Bool()
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val currentpc = UFix(width = VADDR_BITS+1)
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@ -49,6 +48,7 @@ class IOCPUFrontend(implicit conf: ICacheConfig) extends Bundle {
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val req = new PipeIO()(new FrontendReq)
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val resp = new FIFOIO()(new FrontendResp).flip
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val ptw = new IOTLBPTW().flip
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val invalidate = Bool(OUTPUT)
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}
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class Frontend(implicit c: ICacheConfig) extends Component
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@ -97,7 +97,7 @@ class Frontend(implicit c: ICacheConfig) extends Component
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btb.io.clr := !io.cpu.req.bits.taken
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btb.io.correct_pc := io.cpu.req.bits.currentpc
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btb.io.correct_target := io.cpu.req.bits.pc
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btb.io.invalidate := io.cpu.req.bits.invalidate || io.cpu.ptw.invalidate
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btb.io.invalidate := io.cpu.invalidate || io.cpu.ptw.invalidate
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tlb.io.ptw <> io.cpu.ptw
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tlb.io.req.valid := !stall && !icmiss
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@ -109,7 +109,7 @@ class Frontend(implicit c: ICacheConfig) extends Component
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icache.io.mem <> io.mem
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icache.io.req.valid := !stall && !s0_same_block
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icache.io.req.bits.idx := Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)
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icache.io.req.bits.invalidate := io.cpu.req.bits.invalidate
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icache.io.invalidate := io.cpu.invalidate
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icache.io.req.bits.ppn := tlb.io.resp.ppn
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icache.io.req.bits.kill := io.cpu.req.valid || tlb.io.resp.miss
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icache.io.resp.ready := !stall && !s1_same_block
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@ -127,7 +127,6 @@ class ICache(implicit c: ICacheConfig) extends Component
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val io = new Bundle {
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val req = new PipeIO()(new Bundle {
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val idx = UFix(width = PGIDX_BITS)
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val invalidate = Bool()
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val ppn = UFix(width = PPN_BITS) // delayed one cycle
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val kill = Bool() // delayed one cycle
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}).flip
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@ -135,6 +134,7 @@ class ICache(implicit c: ICacheConfig) extends Component
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val data = Bits(width = c.ibytes*8)
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val datablock = Bits(width = c.databits)
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})
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val invalidate = Bool(INPUT)
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val mem = new ioUncachedRequestor
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}
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@ -153,10 +153,10 @@ class ICache(implicit c: ICacheConfig) extends Component
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val s1_addr = Cat(io.req.bits.ppn, s1_pgoff).toUFix
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val s1_tag = s1_addr(c.tagbits+c.untagbits-1,c.untagbits)
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val s0_valid = io.req.valid && rdy || s1_valid && stall && !io.req.bits.kill
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val s0_valid = io.req.valid || s1_valid && stall
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val s0_pgoff = Mux(io.req.valid, io.req.bits.idx, s1_pgoff)
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s1_valid := s0_valid
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s1_valid := io.req.valid && rdy || s1_valid && stall && !io.req.bits.kill
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when (io.req.valid && rdy) {
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s1_pgoff := s0_pgoff
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}
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@ -191,7 +191,7 @@ class ICache(implicit c: ICacheConfig) extends Component
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when (refill_done && !invalidated) {
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vb_array := vb_array.bitSet(Cat(repl_way, s2_idx), Bool(true))
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}
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when (io.req.bits.invalidate) {
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when (io.invalidate) {
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vb_array := Bits(0)
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invalidated := Bool(true)
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}
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@ -248,6 +248,7 @@ class ICache(implicit c: ICacheConfig) extends Component
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io.mem.xact_init.valid := (state === s_request) && finish_q.io.enq.ready
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io.mem.xact_init.bits := c.co.getUncachedReadTransactionInit(s2_addr >> UFix(c.offbits), UFix(0))
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io.mem.xact_finish <> finish_q.io.deq
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io.mem.xact_rep.ready := Bool(true)
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// control state machine
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switch (state) {
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