 Andrew Waterman
|
1b030777ce
|
Remove vestigial control signal
|
2014-03-24 04:36:12 -07:00 |
|
|
Andrew Waterman
|
5996418021
|
Fix exception behavior of fmin/fmax
|
2014-03-18 18:36:51 -07:00 |
|
|
Andrew Waterman
|
54cbf0c4f1
|
Add (unused) RV32 CSRs
|
2014-03-15 17:33:17 -07:00 |
|
|
Andrew Waterman
|
943d7ac80a
|
Use LinkedHashSet/Map for simpler determinism
|
2014-03-15 17:31:48 -07:00 |
|
|
Andrew Waterman
|
a0389645b7
|
New FP encoding; improved FP implementation
|
2014-03-11 18:58:24 -07:00 |
|
|
Andrew Waterman
|
00bc1a2293
|
Add fclass.{s|d} instructions
|
2014-03-10 16:59:24 -07:00 |
|
|
Andrew Waterman
|
9f2e16c58a
|
Fix D$ arbiter for >2 inputs
|
2014-03-04 16:32:17 -08:00 |
|
|
Andrew Waterman
|
fa75f6e81e
|
Fix null pointer exception when HAS_FPU=false
|
2014-03-04 16:32:09 -08:00 |
|
|
Andrew Waterman
|
c7110c8389
|
Make FPU pipeline depths configurable
|
2014-02-28 13:39:59 -08:00 |
|
|
Andrew Waterman
|
8e3ca609f7
|
Renumber uarch CSRs into custom CSR space
|
2014-02-14 17:40:00 -08:00 |
|
|
Andrew Waterman
|
a09ff9fdc7
|
Revert to old AUIPC definition
|
2014-02-10 19:04:42 -08:00 |
|
|
Andrew Waterman
|
1456170c6d
|
Always stall decode on RoCC -> FENCE; never stall on RoCC -> deferred AMO.RL fence
|
2014-02-06 12:01:49 -08:00 |
|
|
Andrew Waterman
|
eca8c99f44
|
Ignore rocc interrupt line when no rocc is present
|
2014-02-06 03:06:55 -08:00 |
|
|
Andrew Waterman
|
e7a726fbac
|
Make uarch counters read-only
|
2014-02-06 01:48:56 -08:00 |
|
|
Andrew Waterman
|
62e9313aef
|
Add 16 microarchitectural counters
|
2014-02-06 00:13:02 -08:00 |
|
|
Andrew Waterman
|
febd26f505
|
Correct CSR privilege logic
|
2014-01-31 01:03:17 -08:00 |
|
|
Andrew Waterman
|
0266c1f76a
|
Support retirement width > 1 in CSR file
|
2014-01-24 16:37:40 -08:00 |
|
|
Andrew Waterman
|
267394d3cc
|
Fix CSR interlocks
|
2014-01-24 16:37:40 -08:00 |
|
|
Andrew Waterman
|
1f986d1c96
|
Branches don't care about the ALU input/function
|
2014-01-24 16:37:40 -08:00 |
|
|
Andrew Waterman
|
a1b7774f5d
|
Simplify handling of CAUSE register
|
2014-01-24 16:37:39 -08:00 |
|
|
Andrew Waterman
|
a7489920ce
|
Support CSR atomics on all CSRs, not just STATUS
|
2014-01-21 16:17:39 -08:00 |
|
|
Andrew Waterman
|
6ba2c1abe5
|
Use auto-generated CAUSE constants
|
2014-01-21 15:01:54 -08:00 |
|
|
Andrew Waterman
|
95de358a96
|
More of the same FPU fix
some SP ops followed by DP stores were not working because they
were encoded as subnormals, not NaNs.
|
2014-01-17 14:09:30 -08:00 |
|
|
Andrew Waterman
|
cf38001e98
|
Fix fmv.s.x -> fsd
|
2014-01-17 03:52:35 -08:00 |
|
|
Andrew Waterman
|
57f4d89c90
|
Generate D$ replay_next signals correctly
|
2014-01-16 00:16:09 -08:00 |
|
|
Andrew Waterman
|
6ebdc4d94e
|
Simplify store conditional failure code generation
|
2014-01-16 00:15:48 -08:00 |
|
|
Andrew Waterman
|
31060ea8ae
|
Fix fubar long-latency writeback control logic
Load miss writebacks happening at the same time as multiplication
wasn't working. Hopefully this does it.
|
2014-01-14 04:02:43 -08:00 |
|
|
Andrew Waterman
|
e8486817e6
|
Clean up formatting (i.e. remove tabs, semicolons)
|
2014-01-13 21:43:56 -08:00 |
|
|
Andrew Waterman
|
a50a1f7d50
|
Clean up multiplier/divider stuff
|
2014-01-13 21:37:16 -08:00 |
|
|
Andrew Waterman
|
4d236979bd
|
Fix very far forward JALs
We were sign-extending from the wrong bit, causing a backwards jump.
|
2014-01-13 00:55:48 -08:00 |
|
|
Andrew Waterman
|
c546f66404
|
Swap JAL/JALR encodings (again)
|
2014-01-13 00:54:49 -08:00 |
|
|
Andrew Waterman
|
07a91bb99a
|
Miscellaneous cleanup
|
2013-12-09 19:53:14 -08:00 |
|
|
Andrew Waterman
|
da3135ac9b
|
Begin integer unit clean-up
...to make it easier to generate the superscalar version of the core.
|
2013-12-09 15:06:13 -08:00 |
|
|
Andrew Waterman
|
16d5250924
|
Correct FP trap behavior on FCSR
|
2013-12-05 04:18:04 -08:00 |
|
|
Andrew Waterman
|
5814a90472
|
Make DecodeLogic interface more flexible
|
2013-12-05 04:16:48 -08:00 |
|
|
Andrew Waterman
|
924261e2b2
|
Update to new privileged ISA... phew
|
2013-11-25 04:35:15 -08:00 |
|
|
Andrew Waterman
|
65b8340cea
|
Mitigate D$ hit -> branch -> NPC critical path
|
2013-11-24 14:21:03 -08:00 |
|
|
Andrew Waterman
|
53f726008b
|
Use Mem instead of Vec[Reg] for TLB
QoR-neutral, improves simulation speed
|
2013-11-24 14:21:02 -08:00 |
|
|
Andrew Waterman
|
12f0369e6e
|
Simplify divide early out circuitry
|
2013-10-29 13:20:40 -07:00 |
|
|
Andrew Waterman
|
b44dafbdca
|
Simplify branch offset mux
|
2013-10-29 13:20:40 -07:00 |
|
|
Andrew Waterman
|
23f7bab4f3
|
Reduce FMA pipeline depths
FMA QoR has improved enough to allow this change.
|
2013-10-29 13:20:40 -07:00 |
|
|
Andrew Waterman
|
ea9d0b771e
|
remove aborts; simplify probes
|
2013-03-19 15:29:40 -07:00 |
|
|
Andrew Waterman
|
78868f6075
|
add config option to trade mul/div area for speed
|
2013-01-06 03:47:17 -08:00 |
|
|
Andrew Waterman
|
ce9f4881d2
|
remove broken multiplier early out
|
2013-01-06 03:47:00 -08:00 |
|
|
Andrew Waterman
|
05f19b21d0
|
merge multiplier and divider
|
2012-12-12 02:22:47 -08:00 |
|
|
Andrew Waterman
|
c921fc34a9
|
merge ALU left and right shifters
|
2012-12-12 02:22:34 -08:00 |
|
|
Andrew Waterman
|
f5c53ce35d
|
add ecc support to d$ data rams
i haven't injected errors yet; it may well be incorrect.
|
2012-12-11 15:58:53 -08:00 |
|
|
Andrew Waterman
|
3f59e439ef
|
fix d$ tag raw hazard
|
2012-12-07 15:14:20 -08:00 |
|
|
Andrew Waterman
|
e9752f1d72
|
pipeline host pcr access
|
2012-12-06 14:22:07 -08:00 |
|
|
Andrew Waterman
|
4dda38204f
|
fix d$ reset bug
|
2012-12-06 03:13:22 -08:00 |
|
|
Andrew Waterman
|
290d3d226c
|
fix AMO and store bypass bugs
thanks, torture tester
|
2012-12-06 02:07:52 -08:00 |
|
|
Andrew Waterman
|
4608660f6e
|
torture revealed a couple bugs
FP loads/stores with certain negative offsets could cause illegal rounding
mode traps, and x's were cropping up in situations that are benign in HW.
|
2012-12-04 05:57:53 -08:00 |
|
|
Andrew Waterman
|
90cae54ac4
|
fix D$ read/write concurrency bug
|
2012-11-27 02:42:27 -08:00 |
|
|
Andrew Waterman
|
9c857b83f0
|
refactor PCR file
|
2012-11-27 01:28:06 -08:00 |
|
|
Andrew Waterman
|
64674d4d39
|
clean up PTW and support PADDR_BITS < VADDR_BITS
|
2012-11-26 20:38:45 -08:00 |
|
|
Andrew Waterman
|
608f65e716
|
don't wastefully read 2x the bits from D$ RAMs
|
2012-11-26 20:34:30 -08:00 |
|
|
Andrew Waterman
|
352bb464b5
|
clock gate X/M and M/W store data registers
|
2012-11-26 20:33:41 -08:00 |
|
|
Andrew Waterman
|
8a6ff5f9aa
|
fix D$ writeback bug
I swear I did this last week... perhaps I am finally losing it!
|
2012-11-25 19:46:48 -08:00 |
|
|
Andrew Waterman
|
de2f28193a
|
get rid of more global constants
|
2012-11-25 04:24:25 -08:00 |
|
|
Andrew Waterman
|
c036cdc1ea
|
add option for 2-cycle load-use delay
|
2012-11-24 22:01:08 -08:00 |
|
|
Andrew Waterman
|
b514c7b725
|
clean up I$ parity code
|
2012-11-24 22:00:43 -08:00 |
|
|
Andrew Waterman
|
55082e45c4
|
add AVec, which automatically infers element type
should consider modifying Vec as such
|
2012-11-24 18:19:28 -08:00 |
|
|
Andrew Waterman
|
2b26082132
|
use 1r1w ram for tags; merge tags & permissions
setting the dirty bit now allocates an MSHR (to reuse the existing datapath)
|
2012-11-20 04:09:26 -08:00 |
|
|
Andrew Waterman
|
72f94d1141
|
fix virtual address sign extension detection
|
2012-11-20 04:06:57 -08:00 |
|
|
Andrew Waterman
|
30038bda8a
|
bypass stores to subsequent loads
since we handle subword stores as RMW operations, this occurs frequently
|
2012-11-20 01:33:32 -08:00 |
|
|
Andrew Waterman
|
29bc361d6c
|
remove global constants; disentangle hwacha a bit
|
2012-11-17 17:24:08 -08:00 |
|
|
Andrew Waterman
|
5a7777fe4d
|
clock gate integer datapath more aggressively
|
2012-11-17 06:48:44 -08:00 |
|
|
Andrew Waterman
|
cc067026a2
|
pipeline D$ response -> FPU regfile
|
2012-11-17 06:48:11 -08:00 |
|
|
Andrew Waterman
|
e68b039133
|
fix misc. D$ control bugs
|
2012-11-17 06:47:27 -08:00 |
|
|
Andrew Waterman
|
dad7b71062
|
provide cmd/addr with cache response
|
2012-11-16 21:26:12 -08:00 |
|
|
Andrew Waterman
|
cb8ac73045
|
provide store data with cache response
|
2012-11-16 21:15:13 -08:00 |
|
|
Andrew Waterman
|
9e010beffe
|
fix D$ refill bug
|
2012-11-16 21:05:29 -08:00 |
|
|
Andrew Waterman
|
8dce89703a
|
new D$ with better QoR and AMO pipelining
Vector unit is disabled because nack handling needs to be fixed.
|
2012-11-16 02:39:33 -08:00 |
|
|
Andrew Waterman
|
a90a1790a5
|
improve tlb qor
|
2012-11-16 01:59:38 -08:00 |
|
|
Andrew Waterman
|
ff8c736d94
|
move icache invalidate out of request bundle
|
2012-11-16 01:55:45 -08:00 |
|
|
Andrew Waterman
|
6d10115b19
|
fix D$ tag width
|
2012-11-15 16:46:39 -08:00 |
|
|
Andrew Waterman
|
4d1ca8ba3a
|
remove more global consts; refactor DTLBs
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
|
2012-11-06 08:13:44 -08:00 |
|
|
Andrew Waterman
|
e76892f758
|
remove more global constants
|
2012-11-06 02:55:45 -08:00 |
|
|
Andrew Waterman
|
c5b93798fb
|
factor out more global constants
|
2012-11-05 23:52:32 -08:00 |
|
|
Andrew Waterman
|
5b20ed71be
|
move rd=0 check into bypass logic
before, the check was in the write enable logic, but moving it obviated
an awkward corner case for mtpcr with rd=0.
|
2012-11-05 01:30:57 -08:00 |
|
|
Andrew Waterman
|
5e103054fd
|
fix bug in quine mccluskey
|
2012-11-05 00:28:25 -08:00 |
|
|
Andrew Waterman
|
e9eca6a95d
|
refactor I$ config; remove Top class
|
2012-11-04 16:59:36 -08:00 |
|
|
Andrew Waterman
|
7380c9fe60
|
aggressively clock gate int and fp datapaths
|
2012-11-04 16:40:14 -08:00 |
|
|
Andrew Waterman
|
bd2d61de03
|
use 8T SRAM for I$; gate clock more aggressively
|
2012-11-04 16:39:25 -08:00 |
|
|
Andrew Waterman
|
fedee6c67d
|
add generic error correcting codes
|
2012-10-30 01:03:47 -07:00 |
|
|
Andrew Waterman
|
5773cbb68a
|
rejigger htif to use UncoreConfiguration
|
2012-10-18 17:26:03 -07:00 |
|
|
Andrew Waterman
|
b9a2af697d
|
turn off HAVE_VEC as it's currently broken
the new I$/frontend needs to be integrated
|
2012-10-16 07:38:19 -07:00 |
|
|
Andrew Waterman
|
0a640f2cc6
|
make DecodeLogic deterministic (hopefully)
|
2012-10-16 04:51:21 -07:00 |
|
|
Andrew Waterman
|
5821900329
|
don't refetch from I$ if on same 16B block
|
2012-10-16 02:24:38 -07:00 |
|
|
Andrew Waterman
|
b955985b38
|
improve divider QoR
|
2012-10-16 02:24:38 -07:00 |
|
|
Andrew Waterman
|
197154c485
|
use BTB for JALR
|
2012-10-16 02:24:37 -07:00 |
|
|
Andrew Waterman
|
fc648d13a1
|
remove old Mux1H; add implicit conversions
|
2012-10-16 02:24:37 -07:00 |
|
|
Andrew Waterman
|
661f8e635b
|
merge I$, ITLB, BTB into Frontend
|
2012-10-16 02:24:37 -07:00 |
|
|
Andrew Waterman
|
fcd69dba98
|
add optional early-out to mul/div
|
2012-10-16 02:24:37 -07:00 |
|
|
Andrew Waterman
|
27ddff1adb
|
simplify and improve multiplier
|
2012-10-16 02:24:37 -07:00 |
|
|
Andrew Waterman
|
ed8cc4a1cf
|
eliminate D$ probe->WB critical path
|
2012-10-04 09:05:14 -07:00 |
|
|
Andrew Waterman
|
897a4e349b
|
fix some LLC control bugs
|
2012-08-06 17:10:04 -07:00 |
|
|
Andrew Waterman
|
e9c35b4923
|
ameliorate DTLB kill->rdy critical path
|
2012-08-06 17:05:05 -07:00 |
|
|
Andrew Waterman
|
b94e6915ab
|
refactor IPIs; use new tohost/fromhost protocol
|
2012-08-03 19:00:34 -07:00 |
|
|
Andrew Waterman
|
6510f020c7
|
fix deadlock in coherence hub
|
2012-08-03 19:00:03 -07:00 |
|