Simplify store conditional failure code generation
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31060ea8ae
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@ -85,7 +85,7 @@ class StoreGen(typ: Bits, addr: Bits, dat: Bits)
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dat)
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}
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class LoadGen(typ: Bits, addr: Bits, dat: Bits)
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class LoadGen(typ: Bits, addr: Bits, dat: Bits, zero: Bool)
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{
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val t = new StoreGen(typ, addr, dat)
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val sign = typ === MT_B || typ === MT_H || typ === MT_W || typ === MT_D
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@ -94,8 +94,8 @@ class LoadGen(typ: Bits, addr: Bits, dat: Bits)
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val word = Cat(Mux(t.word, Fill(32, sign && wordShift(31)), dat(63,32)), wordShift)
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val halfShift = Mux(addr(1), word(31,16), word(15,0))
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val half = Cat(Mux(t.half, Fill(48, sign && halfShift(15)), word(63,16)), halfShift)
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val byteShift = Mux(addr(0), half(15,8), half(7,0))
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val byte = Cat(Mux(t.byte, Fill(56, sign && byteShift(7)), half(63,8)), byteShift)
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val byteShift = Mux(zero, UInt(0), Mux(addr(0), half(15,8), half(7,0)))
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val byte = Cat(Mux(zero || t.byte, Fill(56, sign && byteShift(7)), half(63,8)), byteShift)
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}
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class MSHRReq(implicit conf: DCacheConfig) extends HellaCacheReq {
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@ -1002,7 +1002,7 @@ class HellaCache(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends
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// load data subword mux/sign extension
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val s2_data_word_prebypass = s2_data_uncorrected >> Cat(s2_word_idx, Bits(0,log2Up(conf.databits)))
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val s2_data_word = Mux(s2_store_bypass, s2_store_bypass_data, s2_data_word_prebypass)
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val loadgen = new LoadGen(s2_req.typ, s2_req.addr, s2_data_word)
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val loadgen = new LoadGen(s2_req.typ, s2_req.addr, s2_data_word, s2_sc)
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amoalu.io := s2_req
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amoalu.io.lhs := s2_data_word
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@ -1037,7 +1037,7 @@ class HellaCache(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends
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io.cpu.resp.bits.load_replay_next := s1_replay && (s1_read || s1_sc)
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io.cpu.resp.bits.replay := s2_replay
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io.cpu.resp.bits.data := loadgen.word
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io.cpu.resp.bits.data_subword := Mux(s2_sc, s2_sc_fail, loadgen.byte)
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io.cpu.resp.bits.data_subword := loadgen.byte | s2_sc_fail
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io.cpu.resp.bits.store_data := s2_req.data
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io.cpu.ordered := mshrs.io.fence_rdy && !s1_valid && !s2_valid
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