riscv/rocket-chip
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fix D$ tag width

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This commit is contained in:
Andrew Waterman 2012-11-15 16:45:51 -08:00
parent be1980dd2d
commit 6d10115b19
1 changed files with 4 additions and 1 deletions
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5
rocket/src/main/scala/nbdcache.scala
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@ -18,12 +18,15 @@ case class DCacheConfig(sets: Int, ways: Int, co: CoherencePolicy,
def pgidxbits = PGIDX_BITS
def offbits = OFFSET_BITS
def paddrbits = ppnbits + pgidxbits
def lineaddrbits = ppnbits - offbits
def lineaddrbits = paddrbits - offbits
def idxbits = log2Up(sets)
def waybits = log2Up(ways)
def untagbits = offbits + idxbits
def tagbits = lineaddrbits - idxbits
def ramoffbits = log2Up(MEM_DATA_BITS/8)
def databytes = 8 // assumed by StoreGen/LoadGen/AMOALU
def databits = databytes*8
def wordoffbits = log2Up(databytes)
}
abstract class ReplacementPolicy