merge multiplier and divider
This commit is contained in:
Andrew Waterman
parent
c921fc34a9
commit
05f19b21d0
@ -17,8 +17,8 @@ class ioCtrlDpath extends Bundle()
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val sel_alu2 = UFix(OUTPUT, 3);
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val fn_dw = Bool(OUTPUT);
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val fn_alu = UFix(OUTPUT, SZ_ALU_FN);
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val mul_val = Bool(OUTPUT);
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val mul_kill = Bool(OUTPUT)
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val div_mul_val = Bool(OUTPUT)
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val div_mul_kill = Bool(OUTPUT)
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val div_val = Bool(OUTPUT);
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val div_kill = Bool(OUTPUT)
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val sel_wa = Bool(OUTPUT);
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@ -47,10 +47,7 @@ class ioCtrlDpath extends Bundle()
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val jalr_eq = Bool(INPUT)
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val ex_br_type = Bits(OUTPUT, SZ_BR)
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val ex_br_taken = Bool(INPUT)
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val div_rdy = Bool(INPUT);
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val div_result_val = Bool(INPUT);
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val mul_rdy = Bool(INPUT);
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val mul_result_val = Bool(INPUT);
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val div_mul_rdy = Bool(INPUT)
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val mem_ll_wb = Bool(INPUT)
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val mem_ll_waddr = UFix(INPUT, 5)
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val ex_waddr = UFix(INPUT, 5); // write addr from execute stage
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@ -359,8 +356,7 @@ class Control(implicit conf: RocketConfiguration) extends Component
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val ex_reg_flush_inst = Reg(resetVal = Bool(false))
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val ex_reg_jalr = Reg(resetVal = Bool(false))
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val ex_reg_btb_hit = Reg(resetVal = Bool(false))
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val ex_reg_div_val = Reg(resetVal = Bool(false))
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val ex_reg_mul_val = Reg(resetVal = Bool(false))
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val ex_reg_div_mul_val = Reg(resetVal = Bool(false))
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val ex_reg_mem_val = Reg(resetVal = Bool(false))
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val ex_reg_xcpt = Reg(resetVal = Bool(false))
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val ex_reg_fp_val = Reg(resetVal = Bool(false))
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@ -379,8 +375,7 @@ class Control(implicit conf: RocketConfiguration) extends Component
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val mem_reg_wen = Reg(resetVal = Bool(false))
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val mem_reg_fp_wen = Reg(resetVal = Bool(false))
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val mem_reg_flush_inst = Reg(resetVal = Bool(false))
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val mem_reg_div_val = Reg(resetVal = Bool(false))
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val mem_reg_mul_val = Reg(resetVal = Bool(false))
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val mem_reg_div_mul_val = Reg(resetVal = Bool(false))
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val mem_reg_mem_val = Reg(resetVal = Bool(false))
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val mem_reg_xcpt = Reg(resetVal = Bool(false))
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val mem_reg_fp_val = Reg(resetVal = Bool(false))
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@ -479,8 +474,7 @@ class Control(implicit conf: RocketConfiguration) extends Component
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when (ctrl_killd) {
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ex_reg_jalr := Bool(false)
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ex_reg_btb_hit := Bool(false);
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ex_reg_div_val := Bool(false);
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ex_reg_mul_val := Bool(false);
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ex_reg_div_mul_val := Bool(false)
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ex_reg_mem_val := Bool(false);
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ex_reg_valid := Bool(false);
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ex_reg_wen := Bool(false);
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@ -499,8 +493,7 @@ class Control(implicit conf: RocketConfiguration) extends Component
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ex_reg_br_type := id_br_type;
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ex_reg_jalr := id_jalr
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ex_reg_btb_hit := io.imem.resp.bits.taken
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ex_reg_div_val := id_div_val
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ex_reg_mul_val := id_mul_val
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ex_reg_div_mul_val := id_mul_val || id_div_val
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ex_reg_mem_val := id_mem_val.toBool;
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ex_reg_valid := Bool(true)
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ex_reg_pcr := id_pcr
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@ -521,8 +514,7 @@ class Control(implicit conf: RocketConfiguration) extends Component
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val wb_dcache_miss = wb_reg_mem_val && !io.dmem.resp.valid
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val replay_ex = wb_dcache_miss && ex_reg_load_use || mem_reg_flush_inst ||
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ex_reg_mem_val && !io.dmem.req.ready ||
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ex_reg_div_val && !io.dpath.div_rdy ||
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ex_reg_mul_val && !io.dpath.mul_rdy ||
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ex_reg_div_mul_val && !io.dpath.div_mul_rdy ||
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mem_reg_replay_next
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ctrl_killx := take_pc_wb || replay_ex
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@ -535,8 +527,7 @@ class Control(implicit conf: RocketConfiguration) extends Component
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mem_reg_replay := replay_ex && !take_pc_wb;
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mem_reg_xcpt_interrupt := ex_reg_xcpt_interrupt && !take_pc_wb
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when (ex_xcpt) { mem_reg_cause := ex_cause }
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mem_reg_div_val := ex_reg_div_val && io.dpath.div_rdy
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mem_reg_mul_val := ex_reg_mul_val && io.dpath.mul_rdy
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mem_reg_div_mul_val := ex_reg_div_mul_val && io.dpath.div_mul_rdy
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when (ctrl_killx) {
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mem_reg_valid := Bool(false);
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@ -603,7 +594,7 @@ class Control(implicit conf: RocketConfiguration) extends Component
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wb_reg_eret := mem_reg_eret && !mem_reg_replay
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wb_reg_flush_inst := mem_reg_flush_inst;
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wb_reg_mem_val := mem_reg_mem_val
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wb_reg_div_mul_val := mem_reg_div_val || mem_reg_mul_val
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wb_reg_div_mul_val := mem_reg_div_mul_val
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wb_reg_fp_val := mem_reg_fp_val
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wb_reg_replay_next := mem_reg_replay_next
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}
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@ -674,7 +665,7 @@ class Control(implicit conf: RocketConfiguration) extends Component
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io.fpu.dec.ren2 && id_raddr2 === io.dpath.ex_waddr ||
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io.fpu.dec.ren3 && id_raddr3 === io.dpath.ex_waddr ||
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io.fpu.dec.wen && id_waddr === io.dpath.ex_waddr)
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val id_ex_hazard = data_hazard_ex && (ex_reg_mem_val || ex_reg_div_val || ex_reg_mul_val || ex_reg_fp_val) ||
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val id_ex_hazard = data_hazard_ex && (ex_reg_mem_val || ex_reg_div_mul_val || ex_reg_fp_val) ||
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fp_data_hazard_ex && (ex_reg_mem_val || ex_reg_fp_val)
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// stall for RAW/WAW hazards on LB/LH and mul/div in memory stage.
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@ -691,7 +682,7 @@ class Control(implicit conf: RocketConfiguration) extends Component
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io.fpu.dec.ren2 && id_raddr2 === io.dpath.mem_waddr ||
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io.fpu.dec.ren3 && id_raddr3 === io.dpath.mem_waddr ||
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io.fpu.dec.wen && id_waddr === io.dpath.mem_waddr)
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val id_mem_hazard = data_hazard_mem && (mem_reg_mem_val && mem_mem_cmd_bh || mem_reg_div_val || mem_reg_mul_val || mem_reg_fp_val) ||
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val id_mem_hazard = data_hazard_mem && (mem_reg_mem_val && mem_mem_cmd_bh || mem_reg_div_mul_val || mem_reg_fp_val) ||
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fp_data_hazard_mem && mem_reg_fp_val
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id_load_use := mem_reg_mem_val && (data_hazard_mem || fp_data_hazard_mem)
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@ -731,10 +722,8 @@ class Control(implicit conf: RocketConfiguration) extends Component
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io.dpath.sel_alu2 := id_sel_alu2.toUFix
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io.dpath.fn_dw := id_fn_dw.toBool;
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io.dpath.fn_alu := id_fn_alu.toUFix
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io.dpath.div_val := ex_reg_div_val
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io.dpath.div_kill := mem_reg_div_val && killm_common
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io.dpath.mul_val := ex_reg_mul_val
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io.dpath.mul_kill := mem_reg_mul_val && killm_common
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io.dpath.div_mul_val := ex_reg_div_mul_val
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io.dpath.div_mul_kill := mem_reg_div_mul_val && killm_common
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io.dpath.ex_fp_val:= ex_reg_fp_val;
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io.dpath.mem_fp_val:= mem_reg_fp_val;
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io.dpath.ex_jalr := ex_reg_jalr
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@ -4,62 +4,83 @@ import Chisel._
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import Node._
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import Constants._
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import ALU._
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import Util._
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class Divider(earlyOut: Boolean = false)(implicit conf: RocketConfiguration) extends Component {
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class MulDiv(mulUnroll: Int = 1, earlyOut: Boolean = false)(implicit conf: RocketConfiguration) extends Component {
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val io = new MultiplierIO
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val w = io.req.bits.in1.getWidth
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val mulw = (w+1+mulUnroll-1)/mulUnroll*mulUnroll
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val s_ready :: s_neg_inputs :: s_busy :: s_neg_outputs :: s_done :: Nil = Enum(5) { UFix() };
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val s_ready :: s_neg_inputs :: s_mul_busy :: s_div_busy :: s_move_rem :: s_neg_output :: s_done :: Nil = Enum(7) { UFix() };
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val state = Reg(resetVal = s_ready);
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val count = Reg() { UFix(width = log2Up(w+1)) }
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val divby0 = Reg() { Bool() };
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val neg_quo = Reg() { Bool() };
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val neg_rem = Reg() { Bool() };
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val rem = Reg() { Bool() };
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val half = Reg() { Bool() };
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val r_req = Reg{io.req.bits.clone}
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val divisor = Reg() { Bits() }
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val remainder = Reg() { Bits(width = 2*w+1) }
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val subtractor = remainder(2*w,w) - divisor
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val dw = io.req.bits.dw
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val fn = io.req.bits.fn
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val tc = isMulFN(fn, FN_DIV) || isMulFN(fn, FN_REM)
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val req = Reg{io.req.bits.clone}
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val count = Reg{UFix(width = log2Up(w+1))}
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val divby0 = Reg{Bool()}
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val neg_out = Reg{Bool()}
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val divisor = Reg{Bits(width = w+1)} // div only needs w bits
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val remainder = Reg{Bits(width = 2*mulw+1)} // div only needs 2*w+1 bits
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val lhs_sign = tc && Mux(dw === DW_64, io.req.bits.in1(w-1), io.req.bits.in1(w/2-1))
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val lhs_hi = Mux(dw === DW_64, io.req.bits.in1(w-1,w/2), Fill(w/2, lhs_sign))
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val lhs_in = Cat(lhs_hi, io.req.bits.in1(w/2-1,0))
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val rhs_sign = tc && Mux(dw === DW_64, io.req.bits.in2(w-1), io.req.bits.in2(w/2-1))
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val rhs_hi = Mux(dw === DW_64, io.req.bits.in2(w-1,w/2), Fill(w/2, rhs_sign))
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val rhs_in = Cat(rhs_hi, io.req.bits.in2(w/2-1,0))
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def sext(x: Bits, cmds: Vec[Bits]) = {
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val sign = Mux(io.req.bits.dw === DW_64, x(w-1), x(w/2-1)) && cmds.contains(io.req.bits.fn)
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val hi = Mux(io.req.bits.dw === DW_64, x(w-1,w/2), Fill(w/2, sign))
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(Cat(hi, x(w/2-1,0)), sign)
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}
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val (lhs_in, lhs_sign) = sext(io.req.bits.in1, AVec(FN_DIV, FN_REM, FN_MULH, FN_MULHSU))
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val (rhs_in, rhs_sign) = sext(io.req.bits.in2, AVec(FN_DIV, FN_REM, FN_MULH))
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val subtractor = remainder(2*w,w) - divisor(w-1,0)
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when (state === s_neg_inputs) {
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state := s_busy
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state := s_div_busy
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when (remainder(w-1)) {
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remainder := Cat(remainder(2*w, w), -remainder(w-1,0))
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remainder := -remainder(w-1,0)
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}
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when (divisor(w-1)) {
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when (divisor(w-1) && !AVec(FN_MULHU, FN_MULHSU).contains(req.fn)) {
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divisor := subtractor(w-1,0)
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}
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}
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when (state === s_neg_outputs) {
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when (state === s_neg_output) {
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remainder := -remainder(w-1,0)
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state := s_done
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when (neg_rem && neg_quo && !divby0) {
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remainder := Cat(-remainder(2*w, w+1), remainder(w), -remainder(w-1,0))
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}
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when (state === s_move_rem) {
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remainder := remainder(2*w, w+1)
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state := Mux(neg_out, s_neg_output, s_done)
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}
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when (state === s_mul_busy) {
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val carryIn = remainder(w)
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val mplier = Cat(remainder(2*mulw,w+1),remainder(w-1,0)).toFix
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val mpcand = divisor.toFix
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val prod = mplier(mulUnroll-1,0) * mpcand + Mux(carryIn, mpcand, Fix(0))
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val sum = Cat(mplier(2*mulw-1,mulw) + prod, mplier(mulw-1,mulUnroll))
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val carryOut = mplier(mulUnroll-1)
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remainder := Cat(sum(sum.getWidth-1,w), carryOut, sum(w-1,0)).toFix
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val cycles = mulw/mulUnroll
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val shift1 = (UFix(cycles)-count)*mulUnroll
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val shift = shift1(log2Up(w)-1,0)
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val mask = (UFix(1) << shift) - 1
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val eOut = shift1 < w && !((mplier(w-1,0).toBits ^ carryIn.toFix) & mask).orR
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val shifted = mplier >> shift
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when (Bool(earlyOut) && eOut) {
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remainder := Cat(shifted(sum.getWidth-1,w), carryOut, shifted(w-1,0)).toFix
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}
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.elsewhen (neg_quo && !divby0) {
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remainder := Cat(remainder(2*w, w), -remainder(w-1,0))
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}
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.elsewhen (neg_rem) {
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remainder := Cat(-remainder(2*w, w+1), remainder(w,0))
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count := count + 1
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when (count === cycles-1 || Bool(earlyOut) && eOut) {
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state := s_done
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when (AVec(FN_MULH, FN_MULHU, FN_MULHSU) contains req.fn) {
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state := s_move_rem
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}
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}
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}
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when (state === s_busy) {
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when (state === s_div_busy) {
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when (count === UFix(w)) {
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state := Mux(neg_quo || neg_rem, s_neg_outputs, s_done)
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state := Mux(neg_out && !divby0, s_neg_output, s_done)
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when (AVec(FN_REM, FN_REMU) contains req.fn) {
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state := s_move_rem
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}
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}
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count := count + UFix(1)
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@ -69,13 +90,104 @@ class Divider(earlyOut: Boolean = false)(implicit conf: RocketConfiguration) ext
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val divisorMSB = Log2(divisor, w)
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val dividendMSB = Log2(remainder(w-1,0), w)
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val eOutPos = UFix(w-1, log2Up(2*w)) + divisorMSB
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val eOut = count === UFix(0) && eOutPos > dividendMSB && (divisorMSB != UFix(0) || divisor(0))
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val eOutPos = UFix(w-1, log2Up(2*w)) + divisorMSB - dividendMSB
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val eOut = count === UFix(0) && eOutPos > 0 && (divisorMSB != UFix(0) || divisor(0))
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when (Bool(earlyOut) && eOut) {
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val eOutDist = eOutPos - dividendMSB
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val shift = Mux(divisorMSB >= dividendMSB, UFix(w-1), eOutDist(log2Up(w)-1,0))
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val shift = eOutPos(log2Up(w)-1,0)
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remainder := remainder(w-1,0) << shift
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count := shift
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when (eOutPos(log2Up(w))) {
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remainder := remainder(w-1,0) << w-1
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count := w-1
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}
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}
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}
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when (io.resp.fire() || io.kill) {
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state := s_ready
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}
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when (io.req.fire()) {
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val isMul = AVec(FN_MUL, FN_MULH, FN_MULHU, FN_MULHSU).contains(io.req.bits.fn)
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val isRem = AVec(FN_REM, FN_REMU).contains(io.req.bits.fn)
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state := Mux(isMul, s_mul_busy, Mux(lhs_sign || rhs_sign, s_neg_inputs, s_div_busy))
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count := UFix(0)
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neg_out := !isMul && Mux(isRem, lhs_sign, lhs_sign != rhs_sign)
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divby0 := true
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divisor := Cat(rhs_sign, rhs_in)
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remainder := Cat(Fill(mulw-w, isMul && lhs_sign), Bool(false), lhs_in)
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req := io.req.bits
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}
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io.resp.bits := req
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io.resp.bits.data := Mux(req.dw === DW_32, Cat(Fill(w/2, remainder(w/2-1)), remainder(w/2-1,0)), remainder(w-1,0))
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io.resp.valid := state === s_done
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io.req.ready := state === s_ready
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}
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class Divider(earlyOut: Boolean = false)(implicit conf: RocketConfiguration) extends Component {
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val io = new MultiplierIO
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val w = io.req.bits.in1.getWidth
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val s_ready :: s_neg_inputs :: s_busy :: s_move_rem :: s_neg_output :: s_done :: Nil = Enum(6) { UFix() };
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val state = Reg(resetVal = s_ready);
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val count = Reg() { UFix(width = log2Up(w+1)) }
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val divby0 = Reg() { Bool() };
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val neg_out = Reg() { Bool() };
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val r_req = Reg{io.req.bits.clone}
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val divisor = Reg() { Bits() }
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val remainder = Reg() { Bits(width = 2*w+1) }
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val subtractor = remainder(2*w,w) - divisor
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def sext(x: Bits, cmds: Vec[Bits]) = {
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val sign = Mux(io.req.bits.dw === DW_64, x(w-1), x(w/2-1)) && cmds.contains(io.req.bits.fn)
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val hi = Mux(io.req.bits.dw === DW_64, x(w-1,w/2), Fill(w/2, sign))
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(Cat(hi, x(w/2-1,0)), sign)
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}
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val (lhs_in, lhs_sign) = sext(io.req.bits.in1, AVec(FN_DIV, FN_REM))
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val (rhs_in, rhs_sign) = sext(io.req.bits.in2, AVec(FN_DIV, FN_REM))
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val r_isRem = isMulFN(r_req.fn, FN_REM) || isMulFN(r_req.fn, FN_REMU)
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when (state === s_neg_inputs) {
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state := s_busy
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when (remainder(w-1)) {
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remainder := -remainder(w-1,0)
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}
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when (divisor(w-1)) {
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divisor := subtractor(w-1,0)
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}
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}
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when (state === s_neg_output) {
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remainder := -remainder(w-1,0)
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state := s_done
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}
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when (state === s_move_rem) {
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remainder := remainder(2*w, w+1)
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state := Mux(neg_out, s_neg_output, s_done)
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}
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when (state === s_busy) {
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when (count === UFix(w)) {
|
||||
state := Mux(r_isRem, s_move_rem, Mux(neg_out && !divby0, s_neg_output, s_done))
|
||||
}
|
||||
count := count + UFix(1)
|
||||
|
||||
val msb = subtractor(w)
|
||||
divby0 := divby0 && !msb
|
||||
remainder := Cat(Mux(msb, remainder(2*w-1,w), subtractor(w-1,0)), remainder(w-1,0), !msb)
|
||||
|
||||
val divisorMSB = Log2(divisor, w)
|
||||
val dividendMSB = Log2(remainder(w-1,0), w)
|
||||
val eOutPos = UFix(w-1, log2Up(2*w)) + divisorMSB - dividendMSB
|
||||
val eOut = count === UFix(0) && eOutPos > 0 && (divisorMSB != UFix(0) || divisor(0))
|
||||
when (Bool(earlyOut) && eOut) {
|
||||
val shift = eOutPos(log2Up(w)-1,0)
|
||||
remainder := remainder(w-1,0) << shift
|
||||
count := shift
|
||||
when (eOutPos(log2Up(w))) {
|
||||
remainder := remainder(w-1,0) << w-1
|
||||
count := w-1
|
||||
}
|
||||
}
|
||||
}
|
||||
when (io.resp.fire() || io.kill) {
|
||||
@ -84,20 +196,15 @@ class Divider(earlyOut: Boolean = false)(implicit conf: RocketConfiguration) ext
|
||||
when (io.req.fire()) {
|
||||
state := Mux(lhs_sign || rhs_sign, s_neg_inputs, s_busy)
|
||||
count := UFix(0)
|
||||
half := (dw === DW_32);
|
||||
neg_quo := lhs_sign != rhs_sign
|
||||
neg_rem := lhs_sign
|
||||
rem := isMulFN(fn, FN_REM) || isMulFN(fn, FN_REMU)
|
||||
divby0 := Bool(true);
|
||||
neg_out := Mux(AVec(FN_REM, FN_REMU).contains(io.req.bits.fn), lhs_sign, lhs_sign != rhs_sign)
|
||||
divby0 := true
|
||||
divisor := rhs_in
|
||||
remainder := lhs_in
|
||||
r_req := io.req.bits
|
||||
}
|
||||
|
||||
val result = Mux(rem, remainder(w+w, w+1), remainder(w-1,0))
|
||||
|
||||
io.resp.bits := r_req
|
||||
io.resp.bits.data := Mux(half, Cat(Fill(w/2, result(w/2-1)), result(w/2-1,0)), result)
|
||||
io.resp.bits.data := Mux(r_req.dw === DW_32, Cat(Fill(w/2, remainder(w/2-1)), remainder(w/2-1,0)), remainder(w-1,0))
|
||||
io.resp.valid := state === s_done
|
||||
io.req.ready := state === s_ready
|
||||
}
|
||||
|
||||
@ -158,31 +158,17 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
|
||||
alu.io.in2 := ex_op2.toUFix
|
||||
alu.io.in1 := ex_rs1.toUFix
|
||||
|
||||
// divider
|
||||
val div = new Divider(earlyOut = true)
|
||||
div.io.req.valid := io.ctrl.div_val
|
||||
// multiplier and divider
|
||||
val div = new MulDiv(mulUnroll = 4, earlyOut = true)
|
||||
div.io.req.valid := io.ctrl.div_mul_val
|
||||
div.io.req.bits.dw := ex_reg_ctrl_fn_dw
|
||||
div.io.req.bits.fn := ex_reg_ctrl_fn_alu
|
||||
div.io.req.bits.in1 := ex_rs1
|
||||
div.io.req.bits.in2 := ex_rs2
|
||||
div.io.req.bits.tag := ex_reg_waddr
|
||||
div.io.kill := io.ctrl.div_kill
|
||||
div.io.kill := io.ctrl.div_mul_kill
|
||||
div.io.resp.ready := Bool(true)
|
||||
io.ctrl.div_rdy := div.io.req.ready
|
||||
io.ctrl.div_result_val := div.io.resp.valid
|
||||
|
||||
// multiplier
|
||||
val mul = new Multiplier(unroll = 4, earlyOut = true)
|
||||
mul.io.req.valid := io.ctrl.mul_val
|
||||
mul.io.req.bits.dw := ex_reg_ctrl_fn_dw
|
||||
mul.io.req.bits.fn := ex_reg_ctrl_fn_alu
|
||||
mul.io.req.bits.in1 := ex_rs1
|
||||
mul.io.req.bits.in2 := ex_rs2
|
||||
mul.io.req.bits.tag := ex_reg_waddr
|
||||
mul.io.kill := io.ctrl.mul_kill
|
||||
mul.io.resp.ready := Bool(true)
|
||||
io.ctrl.mul_rdy := mul.io.req.ready
|
||||
io.ctrl.mul_result_val := mul.io.resp.valid
|
||||
io.ctrl.div_mul_rdy := div.io.req.ready
|
||||
|
||||
io.fpu.fromint_data := ex_rs1
|
||||
io.ctrl.ex_waddr := ex_reg_waddr
|
||||
@ -266,17 +252,10 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
|
||||
val dmem_resp_replay = io.dmem.resp.bits.replay && dmem_resp_xpu
|
||||
|
||||
val mem_ll_wdata = Bits()
|
||||
mem_ll_wdata := mul.io.resp.bits.data
|
||||
io.ctrl.mem_ll_waddr := mul.io.resp.bits.tag
|
||||
io.ctrl.mem_ll_wb := mul.io.resp.valid
|
||||
when (div.io.resp.valid) {
|
||||
mul.io.resp.ready := Bool(false)
|
||||
mem_ll_wdata := div.io.resp.bits.data
|
||||
io.ctrl.mem_ll_waddr := div.io.resp.bits.tag
|
||||
io.ctrl.mem_ll_wb := Bool(true)
|
||||
}
|
||||
mem_ll_wdata := div.io.resp.bits.data
|
||||
io.ctrl.mem_ll_waddr := div.io.resp.bits.tag
|
||||
io.ctrl.mem_ll_wb := div.io.resp.valid
|
||||
when (dmem_resp_replay) {
|
||||
mul.io.resp.ready := Bool(false)
|
||||
div.io.resp.ready := Bool(false)
|
||||
mem_ll_wdata := io.dmem.resp.bits.data_subword
|
||||
io.ctrl.mem_ll_waddr := dmem_resp_waddr
|
||||
|
||||
@ -9,17 +9,17 @@ object ALU
|
||||
{
|
||||
val SZ_ALU_FN = 4
|
||||
val FN_X = Bits("b????")
|
||||
val FN_ADD = UFix(0)
|
||||
val FN_SL = UFix(1)
|
||||
val FN_XOR = UFix(4)
|
||||
val FN_OR = UFix(6)
|
||||
val FN_AND = UFix(7)
|
||||
val FN_SR = UFix(5)
|
||||
val FN_SUB = UFix(8)
|
||||
val FN_SLT = UFix(10)
|
||||
val FN_SLTU = UFix(11)
|
||||
val FN_SRA = UFix(13)
|
||||
val FN_OP2 = UFix(15)
|
||||
val FN_ADD = Bits(0)
|
||||
val FN_SL = Bits(1)
|
||||
val FN_XOR = Bits(4)
|
||||
val FN_OR = Bits(6)
|
||||
val FN_AND = Bits(7)
|
||||
val FN_SR = Bits(5)
|
||||
val FN_SUB = Bits(8)
|
||||
val FN_SLT = Bits(10)
|
||||
val FN_SLTU = Bits(11)
|
||||
val FN_SRA = Bits(13)
|
||||
val FN_OP2 = Bits(15)
|
||||
|
||||
val FN_DIV = FN_XOR
|
||||
val FN_DIVU = FN_SR
|
||||
|
||||
Loading…
Reference in New Issue
Block a user