riscv/rocket-chip
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fix d$ reset bug

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This commit is contained in:
Andrew Waterman 2012-12-06 03:13:22 -08:00
parent 290d3d226c
commit 4dda38204f
1 changed files with 1 additions and 1 deletions
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2
rocket/src/main/scala/nbdcache.scala
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@ -582,7 +582,7 @@ class MetaDataArray(implicit conf: DCacheConfig) extends Component {
io.resp(w).tag := m
}
io.read.ready := Bool(true)
io.read.ready := !rst
io.write.ready := !rst
}