riscv/rocket-chip
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Use Mem instead of Vec[Reg] for TLB

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QoR-neutral, improves simulation speed
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Andrew Waterman 2013-11-24 14:16:53 -08:00
parent 68e270eeb2
commit 53f726008b
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/tlb.scala
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@ -20,7 +20,7 @@ class CAMIO(entries: Int, addr_bits: Int, tag_bits: Int) extends Bundle {
class RocketCAM(entries: Int, tag_bits: Int) extends Module {
val addr_bits = ceil(log(entries)/log(2)).toInt;
val io = new CAMIO(entries, addr_bits, tag_bits);
val cam_tags = Vec.fill(entries){Reg(Bits(width = tag_bits))}
val cam_tags = Mem(Bits(width = tag_bits), entries)
val vb_array = Reg(init=Bits(0, entries))
when (io.write) {