Use auto-generated CAUSE constants
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parent
95de358a96
commit
6ba2c1abe5
@ -433,13 +433,13 @@ class Control(implicit conf: RocketConfiguration) extends Module
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val (id_xcpt, id_cause) = checkExceptions(List(
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(id_interrupt, id_interrupt_cause),
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(io.imem.resp.bits.xcpt_ma, UInt(0)),
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(io.imem.resp.bits.xcpt_if, UInt(1)),
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(!id_int_val || id_csr_invalid, UInt(2)),
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(id_privileged && !io.dpath.status.s, UInt(3)),
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((id_fp_val || id_csr_fp) && !io.dpath.status.ef, UInt(4)),
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(id_syscall, UInt(6)),
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(id_rocc_val && !io.dpath.status.er, UInt(12))))
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(io.imem.resp.bits.xcpt_ma, UInt(Causes.misaligned_fetch)),
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(io.imem.resp.bits.xcpt_if, UInt(Causes.fault_fetch)),
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(!id_int_val || id_csr_invalid, UInt(Causes.illegal_instruction)),
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(id_privileged && !io.dpath.status.s, UInt(Causes.privileged_instruction)),
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((id_fp_val || id_csr_fp) && !io.dpath.status.ef, UInt(Causes.fp_disabled)),
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(id_syscall, UInt(Causes.syscall)),
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(id_rocc_val && !io.dpath.status.er, UInt(Causes.accelerator_disabled))))
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ex_reg_xcpt_interrupt := id_interrupt && !take_pc && io.imem.resp.valid
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when (id_xcpt) { ex_reg_cause := id_cause }
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@ -496,7 +496,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
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val (ex_xcpt, ex_cause) = checkExceptions(List(
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(ex_reg_xcpt_interrupt || ex_reg_xcpt, ex_reg_cause),
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(ex_reg_fp_val && io.fpu.illegal_rm, UInt(2))))
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(ex_reg_fp_val && io.fpu.illegal_rm, UInt(Causes.illegal_instruction))))
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mem_reg_replay := replay_ex && !take_pc_wb
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mem_reg_xcpt_interrupt := ex_reg_xcpt_interrupt && !take_pc_wb && !mem_reg_replay_next
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@ -533,10 +533,10 @@ class Control(implicit conf: RocketConfiguration) extends Module
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val (mem_xcpt, mem_cause) = checkExceptions(List(
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(mem_reg_xcpt_interrupt || mem_reg_xcpt, mem_reg_cause),
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(mem_reg_mem_val && io.dmem.xcpt.ma.ld, UInt( 8)),
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(mem_reg_mem_val && io.dmem.xcpt.ma.st, UInt( 9)),
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(mem_reg_mem_val && io.dmem.xcpt.pf.ld, UInt(10)),
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(mem_reg_mem_val && io.dmem.xcpt.pf.st, UInt(11))))
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(mem_reg_mem_val && io.dmem.xcpt.ma.ld, UInt(Causes.misaligned_load)),
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(mem_reg_mem_val && io.dmem.xcpt.ma.st, UInt(Causes.misaligned_store)),
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(mem_reg_mem_val && io.dmem.xcpt.pf.ld, UInt(Causes.fault_load)),
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(mem_reg_mem_val && io.dmem.xcpt.pf.st, UInt(Causes.fault_store))))
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val dcache_kill_mem = mem_reg_wen && io.dmem.replay_next.valid // structural hazard on writeback port
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val fpu_kill_mem = mem_reg_fp_val && io.fpu.nack_mem
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@ -5,14 +5,14 @@ import Node._
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/* Automatically generated by parse-opcodes */
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object Instructions {
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def JAL = Bits("b?????????????????????????1101111")
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def JALR = Bits("b?????????????????000?????1100111")
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def BEQ = Bits("b?????????????????000?????1100011")
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def BNE = Bits("b?????????????????001?????1100011")
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def BLT = Bits("b?????????????????100?????1100011")
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def BGE = Bits("b?????????????????101?????1100011")
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def BLTU = Bits("b?????????????????110?????1100011")
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def BGEU = Bits("b?????????????????111?????1100011")
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def JALR = Bits("b?????????????????000?????1100111")
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def JAL = Bits("b?????????????????????????1101111")
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def LUI = Bits("b?????????????????????????0110111")
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def AUIPC = Bits("b?????????????????????????0010111")
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def ADDI = Bits("b?????????????????000?????0010011")
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@ -185,6 +185,36 @@ object Instructions {
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def CUSTOM3_RD_RS1 = Bits("b?????????????????110?????1111011")
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def CUSTOM3_RD_RS1_RS2 = Bits("b?????????????????111?????1111011")
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}
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object Causes {
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val misaligned_fetch = 0x0
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val fault_fetch = 0x1
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val illegal_instruction = 0x2
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val privileged_instruction = 0x3
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val fp_disabled = 0x4
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val syscall = 0x6
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val breakpoint = 0x7
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val misaligned_load = 0x8
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val misaligned_store = 0x9
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val fault_load = 0xa
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val fault_store = 0xb
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val accelerator_disabled = 0xc
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val all = {
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val res = collection.mutable.ArrayBuffer[Int]()
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res += misaligned_fetch
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res += fault_fetch
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res += illegal_instruction
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res += privileged_instruction
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res += fp_disabled
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res += syscall
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res += breakpoint
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res += misaligned_load
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res += misaligned_store
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res += fault_load
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res += fault_store
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res += accelerator_disabled
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res.toArray
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}
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}
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object CSRs {
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val fflags = 0x1
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val frm = 0x2
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