riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
Rocket Chip Generator (https://github.com/freechipsproject/rocket-chip)
670 Commits 1 Branch 0 Tags 13 MiB
Scala 93.1%
C++ 2.1%
Python 2%
Makefile 1.2%
Verilog 0.8%
Other 0.7%
53f726008b
Go to file
Andrew Waterman 53f726008b Use Mem instead of Vec[Reg] for TLB 
QoR-neutral, improves simulation speed
2013-11-24 14:21:02 -08:00
rocket/src/main/scala Use Mem instead of Vec[Reg] for TLB 2013-11-24 14:21:02 -08:00