riscv/rocket-chip: Rocket Chip Generator (https://github.com/freechipsproject/rocket-chip) - rocket-chip - Tiband Gitea

riscv/rocket-chip

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Andrew Waterman 53f726008b Use Mem instead of Vec[Reg] for TLB

QoR-neutral, improves simulation speed

2013-11-24 14:21:02 -08:00

rocket/src/main/scala

Use Mem instead of Vec[Reg] for TLB

2013-11-24 14:21:02 -08:00

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