riscv/rocket-chip: Rocket Chip Generator (https://github.com/freechipsproject/rocket-chip) - rocket-chip - Tiband Gitea

riscv/rocket-chip

T

Andrew Waterman 53f726008b Use Mem instead of Vec[Reg] for TLB

QoR-neutral, improves simulation speed

2013-11-24 14:21:02 -08:00

rocket/src/main/scala

Use Mem instead of Vec[Reg] for TLB

2013-11-24 14:21:02 -08:00

Languages

Scala 93.1%

C++ 2.1%

Python 2%

Makefile 1.2%

Verilog 0.8%

Other 0.7%