riscv/rocket-chip
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Rocket Chip Generator (https://github.com/freechipsproject/rocket-chip)
529 Commits 1 Branch 0 Tags 13 MiB
Scala 93.1%
C++ 2.1%
Python 2%
Makefile 1.2%
Verilog 0.8%
Other 0.7%
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Andrew Waterman 2b26082132 use 1r1w ram for tags; merge tags & permissions 
setting the dirty bit now allocates an MSHR (to reuse the existing datapath)
2012-11-20 04:09:26 -08:00
rocket/src/main/scala use 1r1w ram for tags; merge tags & permissions 2012-11-20 04:09:26 -08:00