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riscv
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rocket-chip
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2b26082132550f834e695f3d6ad7dbba81cdedc3
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Andrew Waterman
2b26082132
use 1r1w ram for tags; merge tags & permissions
...
setting the dirty bit now allocates an MSHR (to reuse the existing datapath)
2012-11-20 04:09:26 -08:00
rocket/src/main
/scala
use 1r1w ram for tags; merge tags & permissions
2012-11-20 04:09:26 -08:00
Description
Rocket Chip Generator (
https://github.com/freechipsproject/rocket-chip
)
13
MiB
Languages
Scala
93.1%
C++
2.1%
Python
2%
Makefile
1.2%
Verilog
0.8%
Other
0.7%