riscv/rocket-chip
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Miscellaneous cleanup

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This commit is contained in:
Andrew Waterman
2013-12-09 19:52:47 -08:00
parent da3135ac9b
commit 07a91bb99a
4 changed files with 20 additions and 25 deletions
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6
rocket/src/main/scala/ctrl.scala
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@@ -321,11 +321,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
if (conf.fpu) decode_table ++= FDecode.table
if (!conf.rocc.isEmpty) decode_table ++= RoCCDecode.table
val logic = DecodeLogic(io.dpath.inst, XDecode.decode_default, decode_table)
val cs = logic.map {
case b if b.inputs.head.getClass == classOf[Bool] => b.toBool
case u => u
}
val cs = DecodeLogic(io.dpath.inst, XDecode.decode_default, decode_table)
val (id_int_val: Bool) :: (id_fp_val: Bool) :: (id_rocc_val: Bool) :: id_br_type :: (id_jalr: Bool) :: (id_renx2: Bool) :: (id_renx1: Bool) :: cs0 = cs
val id_sel_alu2 :: id_sel_alu1 :: id_sel_imm :: (id_fn_dw: Bool) :: id_fn_alu :: cs1 = cs0

15
rocket/src/main/scala/decode.scala
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@@ -16,7 +16,7 @@ object DecodeLogic
}
def logic(addr: UInt, addrWidth: Int, cache: scala.collection.mutable.Map[Term,Bool], terms: Seq[Term]) = {
terms.map { t =>
cache.getOrElseUpdate(t, (if (t.mask == 0) addr else addr & Lit(BigInt(2).pow(addrWidth)-(t.mask+1), addrWidth){Bits()}) === Lit(t.value, addrWidth){Bits()})
cache.getOrElseUpdate(t, (if (t.mask == 0) addr else addr & Bits(BigInt(2).pow(addrWidth)-(t.mask+1), addrWidth)) === Bits(t.value, addrWidth))
}.foldLeft(Bool(false))(_||_)
}
def apply[T <: Bits](addr: UInt, default: T, mapping: Iterable[(UInt, T)]): T = {
@@ -48,13 +48,12 @@ object DecodeLogic
default.fromBits(result)
}
def apply[T <: Bits](addr: UInt, default: Iterable[T], mappingIn: Iterable[(UInt, Iterable[T])]): Iterable[T] = {
var mapping = mappingIn
default map { thisDefault =>
val thisMapping = for ((key, values) <- mapping) yield key -> values.head
val res = apply(addr, thisDefault, thisMapping)
mapping = for ((key, values) <- mapping) yield key -> values.tail
res
}
val mapping = collection.mutable.ArrayBuffer.fill(default.size)(collection.mutable.ArrayBuffer[(UInt, T)]())
for ((key, values) <- mappingIn)
for ((value, i) <- values zipWithIndex)
mapping(i) += key -> value
for ((thisDefault, thisMapping) <- default zip mapping)
yield apply(addr, thisDefault, thisMapping)
}
def apply(addr: UInt, trues: Iterable[UInt], falses: Iterable[UInt]): Bool =
apply(addr, Bool.DC, trues.map(_ -> Bool(true)) ++ falses.map(_ -> Bool(false)))

6
rocket/src/main/scala/nbdcache.scala
View File

@@ -276,7 +276,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig, tl: TileLinkConfiguration) exte
io.req_sec_rdy := sec_rdy && rpq.io.enq.ready
val meta_hazard = Reg(init=UInt(0,2))
when (meta_hazard != 0) { meta_hazard := meta_hazard + 1 }
when (meta_hazard != UInt(0)) { meta_hazard := meta_hazard + 1 }
when (io.meta_write.fire()) { meta_hazard := 1 }
io.probe_rdy := !idx_match || (state != s_wb_req && state != s_wb_resp && state != s_meta_clear && meta_hazard === 0)
@@ -574,7 +574,7 @@ class MetaDataArray(implicit conf: DCacheConfig, tl: TileLinkConfiguration) exte
val rst = rst_cnt < conf.sets
when (rst) { rst_cnt := rst_cnt+1 }
val metabits = io.write.bits.data.state.width + conf.tagbits
val metabits = io.write.bits.data.state.getWidth + conf.tagbits
val tags = Mem(UInt(width = metabits*conf.ways), conf.sets, seqRead = true)
when (rst || io.write.valid) {
@@ -992,7 +992,7 @@ class HellaCache(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends
when (s1_clk_en) {
s2_store_bypass := false
when (bypasses.map(_._1).reduce(_||_)) {
s2_store_bypass_data := PriorityMux(bypasses.map(x => (x._1, x._2)))
s2_store_bypass_data := PriorityMux(bypasses)
s2_store_bypass := true
}
}

18
rocket/src/main/scala/util.scala
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@@ -28,19 +28,19 @@ object AVec
object Str
{
def apply(s: String): Bits = {
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
Lit(i, s.length*8){Bits()}
UInt(i, s.length*8)
}
def apply(x: Char): Bits = {
def apply(x: Char): UInt = {
require(validChar(x))
Lit(x, 8){Bits()}
UInt(x.toInt, 8)
}
def apply(x: UInt): Bits = apply(x, 10)
def apply(x: UInt, radix: Int): Bits = {
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = UInt(radix)
val w = x.getWidth
require(w > 0)
@@ -53,8 +53,8 @@ object Str
}
s
}
def apply(x: SInt): Bits = apply(x, 10)
def apply(x: SInt, radix: Int): Bits = {
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < SInt(0)
val abs = x.abs
if (radix != 10) {
@@ -78,7 +78,7 @@ object Str
}
}
private def digit(d: UInt): Bits = Mux(d < UInt(10), Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def digit(d: UInt): UInt = Mux(d < UInt(10), Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}