riscv/rocket-chip
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add option for 2-cycle load-use delay

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This commit is contained in:
Andrew Waterman 2012-11-24 22:01:08 -08:00
parent b514c7b725
commit c036cdc1ea
4 changed files with 9 additions and 6 deletions
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7
rocket/src/main/scala/ctrl.scala
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@ -676,9 +676,10 @@ class Control(implicit conf: RocketConfiguration) extends Component
fp_data_hazard_ex && (ex_reg_mem_val || ex_reg_fp_val)
// stall for RAW/WAW hazards on LB/LH and mul/div in memory stage.
val mem_mem_cmd_bh = if (conf.fastLoadByte) Bool(false) else
(mem_reg_mem_type === MT_B) || (mem_reg_mem_type === MT_BU) ||
(mem_reg_mem_type === MT_H) || (mem_reg_mem_type === MT_HU)
val mem_mem_cmd_bh =
if (!conf.fastLoadWord) Bool(true)
else if (conf.fastLoadByte) Bool(false)
else AVec(MT_B, MT_BU, MT_H, MT_HU) contains mem_reg_mem_type
val data_hazard_mem = mem_reg_wen &&
(id_raddr1 != UFix(0) && id_renx1 && id_raddr1 === io.dpath.mem_waddr ||
id_raddr2 != UFix(0) && id_renx2 && id_raddr2 === io.dpath.mem_waddr ||

4
rocket/src/main/scala/dpath.scala
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@ -135,13 +135,13 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
val dmem_resp_data = if (conf.fastLoadByte) io.dmem.resp.bits.data_subword else io.dmem.resp.bits.data
val ex_rs1 =
Mux(ex_reg_rs1_bypass && ex_reg_rs1_lsb === UFix(3), dmem_resp_data,
Mux(ex_reg_rs1_bypass && ex_reg_rs1_lsb === UFix(3) && Bool(conf.fastLoadWord), dmem_resp_data,
Mux(ex_reg_rs1_bypass && ex_reg_rs1_lsb === UFix(2), wb_reg_wdata,
Mux(ex_reg_rs1_bypass && ex_reg_rs1_lsb === UFix(1), mem_reg_wdata,
Mux(ex_reg_rs1_bypass && ex_reg_rs1_lsb === UFix(0), Bits(0),
Cat(ex_reg_rs1_msb, ex_reg_rs1_lsb)))))
val ex_rs2 =
Mux(ex_reg_rs2_bypass && ex_reg_rs2_lsb === UFix(3), dmem_resp_data,
Mux(ex_reg_rs2_bypass && ex_reg_rs2_lsb === UFix(3) && Bool(conf.fastLoadWord), dmem_resp_data,
Mux(ex_reg_rs2_bypass && ex_reg_rs2_lsb === UFix(2), wb_reg_wdata,
Mux(ex_reg_rs2_bypass && ex_reg_rs2_lsb === UFix(1), mem_reg_wdata,
Mux(ex_reg_rs2_bypass && ex_reg_rs2_lsb === UFix(0), Bits(0),

2
rocket/src/main/scala/nbdcache.scala
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@ -728,7 +728,7 @@ class HellaCache(implicit conf: DCacheConfig) extends Component {
val s1_read = isRead(s1_req.cmd)
val s1_write = isWrite(s1_req.cmd)
val s1_readwrite = s1_read || s1_write
val s1_readwrite = s1_read || s1_write || isPrefetch(s1_req.cmd)
val dtlb = new TLB(8)
dtlb.io.ptw <> io.cpu.ptw

2
rocket/src/main/scala/tile.scala
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@ -9,6 +9,7 @@ import Util._
case class RocketConfiguration(ntiles: Int, co: CoherencePolicyWithUncached,
icache: ICacheConfig, dcache: DCacheConfig,
fpu: Boolean, vec: Boolean,
fastLoadWord: Boolean = true,
fastLoadByte: Boolean = false)
{
val dcacheReqTagBits = 9 // enforce compliance with require()
@ -16,6 +17,7 @@ case class RocketConfiguration(ntiles: Int, co: CoherencePolicyWithUncached,
val nxpr = 32
val nxprbits = log2Up(nxpr)
val rvc = false
if (fastLoadByte) require(fastLoadWord)
}
class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Component(resetSignal)