add ecc support to d$ data rams
i haven't injected errors yet; it may well be incorrect.
This commit is contained in:
Andrew Waterman
parent
3f59e439ef
commit
f5c53ce35d
@ -51,9 +51,7 @@ class ALU(implicit conf: RocketConfiguration) extends Component
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val io = new ALUIO
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// ADD, SUB
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val sub = isSub(io.fn)
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val adder_rhs = Mux(sub, ~io.in2, io.in2)
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val sum = (io.in1 + adder_rhs + sub.toUFix)(63,0)
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val sum = io.in1 + Mux(isSub(io.fn), -io.in2, io.in2)
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// SLT, SLTU
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val less = Mux(io.in1(63) === io.in2(63), sum(63),
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@ -8,8 +8,9 @@ import Util._
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case class DCacheConfig(sets: Int, ways: Int, co: CoherencePolicy,
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nmshr: Int, nrpq: Int, nsdq: Int, ntlb: Int,
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reqtagbits: Int = -1, databits: Int = -1,
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narrowRead: Boolean = true)
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code: Code = new IdentityCode,
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narrowRead: Boolean = true,
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reqtagbits: Int = -1, databits: Int = -1)
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{
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require(isPow2(sets))
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require(isPow2(ways)) // TODO: relax this
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@ -29,6 +30,12 @@ case class DCacheConfig(sets: Int, ways: Int, co: CoherencePolicy,
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def databytes = databits/8
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def wordoffbits = log2Up(databytes)
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def isNarrowRead = narrowRead && databits*ways % MEM_DATA_BITS == 0
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val statebits = 2 // TODO: obtain from coherence policy
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val metabits = statebits + tagbits
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val encdatabits = code.width(databits)
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val encmetabits = code.width(metabits)
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val wordsperrow = MEM_DATA_BITS/databits
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val bitsperrow = wordsperrow*encdatabits
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}
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abstract class ReplacementPolicy
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@ -110,8 +117,8 @@ class DataReadReq(implicit conf: DCacheConfig) extends Bundle {
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class DataWriteReq(implicit conf: DCacheConfig) extends Bundle {
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val way_en = Bits(width = conf.ways)
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val addr = Bits(width = conf.untagbits)
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val wmask = Bits(width = MEM_DATA_BITS/conf.databits)
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val data = Bits(width = MEM_DATA_BITS)
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val wmask = Bits(width = conf.wordsperrow)
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val data = Bits(width = conf.bitsperrow)
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override def clone = new DataWriteReq().asInstanceOf[this.type]
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}
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@ -126,7 +133,7 @@ class WritebackReq(implicit conf: DCacheConfig) extends Bundle {
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}
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class MetaData(implicit conf: DCacheConfig) extends Bundle {
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val state = UFix(width = 2)
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val state = UFix(width = conf.statebits)
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val tag = Bits(width = conf.tagbits)
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override def clone = new MetaData().asInstanceOf[this.type]
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@ -413,7 +420,7 @@ class WritebackUnit(implicit conf: DCacheConfig) extends Component {
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val probe = (new FIFOIO) { new WritebackReq() }.flip
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val meta_read = (new FIFOIO) { new MetaReadReq }
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val data_req = (new FIFOIO) { new DataReadReq() }
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val data_resp = Bits(INPUT, MEM_DATA_BITS)
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val data_resp = Bits(INPUT, conf.bitsperrow)
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val mem_req = (new FIFOIO) { new TransactionInit }
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val mem_req_data = (new FIFOIO) { new TransactionInitData }
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val probe_rep_data = (new FIFOIO) { new ProbeReplyData }
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@ -430,7 +437,7 @@ class WritebackUnit(implicit conf: DCacheConfig) extends Component {
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when (valid) {
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r1_data_req_fired := false
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r2_data_req_fired := r1_data_req_fired
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when (io.data_req.fire()) {
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when (io.data_req.fire() && io.meta_read.fire()) {
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r1_data_req_fired := true
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cnt := cnt + 1
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}
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@ -467,7 +474,7 @@ class WritebackUnit(implicit conf: DCacheConfig) extends Component {
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val fire = valid && cnt < UFix(REFILL_CYCLES)
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io.req.ready := !valid && !io.probe.valid
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io.probe.ready := !valid
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io.data_req.valid := fire && io.meta_read.ready
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io.data_req.valid := fire
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io.data_req.bits.way_en := req.way_en
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io.data_req.bits.addr := Cat(req.idx, cnt(log2Up(REFILL_CYCLES)-1,0)) << conf.ramoffbits
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@ -480,7 +487,7 @@ class WritebackUnit(implicit conf: DCacheConfig) extends Component {
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io.probe_rep_data.valid := r2_data_req_fired && is_probe
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io.probe_rep_data.bits.data := io.data_resp
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io.meta_read.valid := fire && io.data_req.ready
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io.meta_read.valid := fire
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io.meta_read.bits.addr := io.mem_req.bits.addr << conf.offbits
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}
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@ -594,32 +601,31 @@ class DataArray(implicit conf: DCacheConfig) extends Component {
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val io = new Bundle {
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val read = new FIFOIO()(new DataReadReq).flip
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val write = new FIFOIO()(new DataWriteReq).flip
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val resp = Vec(conf.ways){ Bits(OUTPUT, MEM_DATA_BITS) }
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val resp = Vec(conf.ways){ Bits(OUTPUT, conf.bitsperrow) }
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}
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val waddr = io.write.bits.addr >> conf.ramoffbits
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val raddr = io.read.bits.addr >> conf.ramoffbits
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if (conf.isNarrowRead) {
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val waysPerMem = MEM_DATA_BITS/conf.databits
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for (w <- 0 until conf.ways by waysPerMem) {
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val wway_en = io.write.bits.way_en(w+waysPerMem-1,w)
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val rway_en = io.read.bits.way_en(w+waysPerMem-1,w)
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val resp = Vec(MEM_DATA_BITS/conf.databits){Reg{Bits(width = MEM_DATA_BITS)}}
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for (w <- 0 until conf.ways by conf.wordsperrow) {
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val wway_en = io.write.bits.way_en(w+conf.wordsperrow-1,w)
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val rway_en = io.read.bits.way_en(w+conf.wordsperrow-1,w)
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val resp = Vec(conf.wordsperrow){Reg{Bits(width = conf.bitsperrow)}}
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val r_raddr = RegEn(io.read.bits.addr, io.read.valid)
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for (p <- 0 until resp.size) {
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val array = Mem(conf.sets*REFILL_CYCLES, seqRead = true){ Bits(width=MEM_DATA_BITS) }
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val array = Mem(conf.sets*REFILL_CYCLES, seqRead = true){ Bits(width=conf.bitsperrow) }
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when (wway_en.orR && io.write.valid && io.write.bits.wmask(p)) {
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val data = Fill(waysPerMem, io.write.bits.data(conf.databits*(p+1)-1,conf.databits*p))
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val mask = FillInterleaved(conf.databits, wway_en)
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val data = Fill(conf.wordsperrow, io.write.bits.data(conf.encdatabits*(p+1)-1,conf.encdatabits*p))
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val mask = FillInterleaved(conf.encdatabits, wway_en)
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array.write(waddr, data, mask)
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}
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when (rway_en.orR && io.read.valid) {
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resp(p) := array(raddr)
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}
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}
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for (dw <- 0 until waysPerMem) {
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val r = AVec(resp.map(_(conf.databits*(dw+1)-1,conf.databits*dw)))
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for (dw <- 0 until conf.wordsperrow) {
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val r = AVec(resp.map(_(conf.encdatabits*(dw+1)-1,conf.encdatabits*dw)))
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val resp_mux =
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if (r.size == 1) r
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else AVec(r(r_raddr(conf.ramoffbits-1,conf.wordoffbits)), r.tail:_*)
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@ -627,10 +633,10 @@ class DataArray(implicit conf: DCacheConfig) extends Component {
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}
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}
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} else {
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val wmask = FillInterleaved(conf.databits, io.write.bits.wmask)
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val wmask = FillInterleaved(conf.encdatabits, io.write.bits.wmask)
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for (w <- 0 until conf.ways) {
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val rdata = Reg() { Bits() }
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val array = Mem(conf.sets*REFILL_CYCLES, seqRead = true){ Bits(width=MEM_DATA_BITS) }
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val array = Mem(conf.sets*REFILL_CYCLES, seqRead = true){ Bits(width=conf.bitsperrow) }
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when (io.write.bits.way_en(w) && io.write.valid) {
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array.write(waddr, io.write.bits.data, wmask)
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}
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@ -752,12 +758,14 @@ class HellaCache(implicit conf: DCacheConfig) extends Component {
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val s2_valid = Reg(s1_valid_masked, resetVal = Bool(false))
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val s2_req = Reg{io.cpu.req.bits.clone}
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val s2_replay = Reg(s1_replay, resetVal = Bool(false))
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val s2_recycle = Bool()
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val s2_valid_masked = Bool()
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val s3_valid = Reg(resetVal = Bool(false))
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val s3_req = Reg{io.cpu.req.bits.clone}
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val s3_way = Reg{Bits()}
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val s1_recycled = RegEn(s2_recycle, s1_clk_en)
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val s1_read = isRead(s1_req.cmd)
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val s1_write = isWrite(s1_req.cmd)
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val s1_readwrite = s1_read || s1_write || isPrefetch(s1_req.cmd)
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@ -785,6 +793,9 @@ class HellaCache(implicit conf: DCacheConfig) extends Component {
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when (mshr.io.replay.valid) {
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s1_req := mshr.io.replay.bits
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}
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when (s2_recycle) {
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s1_req := s2_req
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}
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val s1_addr = Cat(dtlb.io.resp.ppn, s1_req.addr(conf.pgidxbits-1,0))
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when (s1_clk_en) {
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@ -795,6 +806,7 @@ class HellaCache(implicit conf: DCacheConfig) extends Component {
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when (s1_write) {
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s2_req.data := Mux(s1_replay, mshr.io.replay.bits.data, io.cpu.req.bits.data)
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}
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when (s1_recycled) { s2_req.data := s1_req.data }
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}
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val misaligned =
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@ -809,29 +821,41 @@ class HellaCache(implicit conf: DCacheConfig) extends Component {
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// tags
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val meta = new MetaDataArray
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val metaReadArb = (new Arbiter(4)) { new MetaReadReq }
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val metaReadArb = (new Arbiter(5)) { new MetaReadReq }
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val metaWriteArb = (new Arbiter(2)) { new MetaWriteReq }
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metaReadArb.io.out <> meta.io.read
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metaWriteArb.io.out <> meta.io.write
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// data
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val data = new DataArray
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val readArb = new Arbiter(3)(new DataReadReq)
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val writeArb = new Arbiter(2)(new DataWriteReq)
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val readArb = new Arbiter(4)(new DataReadReq)
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readArb.io.out.ready := !io.mem.xact_rep.valid || io.mem.xact_rep.ready // insert bubble if refill gets blocked
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readArb.io.out <> data.io.read
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writeArb.io.out <> data.io.write
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val writeArb = new Arbiter(2)(new DataWriteReq)
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data.io.write.valid := writeArb.io.out.valid
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writeArb.io.out.ready := data.io.write.ready
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data.io.write.bits := writeArb.io.out.bits
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val wdata_encoded = (0 until conf.wordsperrow).map(i => conf.code.encode(writeArb.io.out.bits.data(conf.databits*(i+1)-1,conf.databits*i)))
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data.io.write.bits.data := AVec(wdata_encoded).toBits
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// tag read for new requests
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metaReadArb.io.in(3).valid := io.cpu.req.valid
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metaReadArb.io.in(3).bits.addr := io.cpu.req.bits.addr
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when (!metaReadArb.io.in(3).ready) { io.cpu.req.ready := Bool(false) }
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metaReadArb.io.in(4).valid := io.cpu.req.valid
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metaReadArb.io.in(4).bits.addr := io.cpu.req.bits.addr
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when (!metaReadArb.io.in(4).ready) { io.cpu.req.ready := Bool(false) }
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// data read for new requests
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readArb.io.in(2).bits.addr := io.cpu.req.bits.addr
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readArb.io.in(2).valid := io.cpu.req.valid
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readArb.io.in(2).bits.way_en := Fix(-1)
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when (!readArb.io.in(2).ready) { io.cpu.req.ready := Bool(false) }
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readArb.io.in(3).bits.addr := io.cpu.req.bits.addr
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readArb.io.in(3).valid := io.cpu.req.valid
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readArb.io.in(3).bits.way_en := Fix(-1)
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when (!readArb.io.in(3).ready) { io.cpu.req.ready := Bool(false) }
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// recycled requests
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metaReadArb.io.in(0).valid := s2_recycle
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metaReadArb.io.in(0).bits.addr := s2_req.addr
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readArb.io.in(0).valid := s2_recycle
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readArb.io.in(0).bits.addr := s2_req.addr
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readArb.io.in(0).bits.way_en := Fix(-1)
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// tag check and way muxing
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def wayMap[T <: Data](f: Int => T)(gen: => T) = Vec((0 until conf.ways).map(i => f(i))){gen}
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@ -844,30 +868,35 @@ class HellaCache(implicit conf: DCacheConfig) extends Component {
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val s2_hit_state = Mux1H(s2_tag_match_way, wayMap((w: Int) => RegEn(meta.io.resp(w).state, s1_clk_en)){Bits()})
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val s2_hit = s2_tag_match && conf.co.isHit(s2_req.cmd, s2_hit_state) && s2_hit_state === conf.co.newStateOnHit(s2_req.cmd, s2_hit_state)
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val s2_data = Vec(conf.ways){Bits(width = MEM_DATA_BITS)}
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val s2_data = Vec(conf.ways){Bits(width = conf.bitsperrow)}
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for (w <- 0 until conf.ways) {
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val regs = Vec(MEM_DATA_BITS/conf.databits){Reg{Bits(width = conf.databits)}}
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val regs = Vec(conf.wordsperrow){Reg{Bits(width = conf.encdatabits)}}
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val en1 = s1_clk_en && s1_tag_eq_way(w)
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for (i <- 0 until regs.size) {
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val en = en1 && (Bool(i == 0 || !conf.isNarrowRead) || s1_writeback)
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when (en) { regs(i) := data.io.resp(w) >> conf.databits*i }
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when (en) { regs(i) := data.io.resp(w) >> conf.encdatabits*i }
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}
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s2_data(w) := Cat(regs.last, regs.init.reverse:_*)
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s2_data(w) := regs.toBits
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}
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val data_resp_mux = Mux1H(s2_tag_match_way, s2_data)
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val s2_data_muxed = Mux1H(s2_tag_match_way, s2_data)
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val s2_data_decoded = (0 until conf.wordsperrow).map(i => conf.code.decode(s2_data_muxed(conf.encdatabits*(i+1)-1,conf.encdatabits*i)))
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val s2_data_corrected = AVec(s2_data_decoded.map(_.corrected)).toBits
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val s2_data_uncorrected = AVec(s2_data_decoded.map(_.uncorrected)).toBits
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val s2_word_idx = if (conf.isNarrowRead) UFix(0) else s2_req.addr(log2Up(conf.wordsperrow*conf.databytes)-1,3)
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val s2_data_correctable = AVec(s2_data_decoded.map(_.correctable)).toBits()(s2_word_idx)
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// store/amo hits
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s3_valid := (s2_valid_masked && s2_hit || s2_replay) && isWrite(s2_req.cmd)
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val amoalu = new AMOALU
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when ((s2_valid || s2_replay) && isWrite(s2_req.cmd)) {
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when ((s2_valid || s2_replay) && (isWrite(s2_req.cmd) || s2_data_correctable)) {
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s3_req := s2_req
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s3_req.data := amoalu.io.out
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s3_req.data := Mux(s2_data_correctable, s2_data_corrected, amoalu.io.out)
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s3_way := s2_tag_match_way
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}
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writeArb.io.in(0).bits.addr := s3_req.addr
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writeArb.io.in(0).bits.wmask := UFix(1) << s3_req.addr(conf.ramoffbits-1,offsetlsb).toUFix
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writeArb.io.in(0).bits.data := Fill(MEM_DATA_BITS/conf.databits, s3_req.data)
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writeArb.io.in(0).bits.data := Fill(conf.wordsperrow, s3_req.data)
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writeArb.io.in(0).valid := s3_valid
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writeArb.io.in(0).bits.way_en := s3_way
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@ -875,15 +904,13 @@ class HellaCache(implicit conf: DCacheConfig) extends Component {
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val replacer = new RandomReplacement
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val s1_replaced_way_en = UFixToOH(replacer.way)
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val s2_replaced_way_en = UFixToOH(RegEn(replacer.way, s1_clk_en))
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val s2_repl_state = Mux1H(s2_replaced_way_en, wayMap((w: Int) => RegEn(meta.io.resp(w).state, s1_clk_en && s1_replaced_way_en(w))){Bits()})
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val s2_repl_tag = Mux1H(s2_replaced_way_en, wayMap((w: Int) => RegEn(meta.io.resp(w).tag, s1_clk_en && s1_replaced_way_en(w))){Bits()})
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val s2_repl_meta = Mux1H(s2_replaced_way_en, wayMap((w: Int) => RegEn(meta.io.resp(w), s1_clk_en && s1_replaced_way_en(w))){new MetaData})
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// miss handling
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mshr.io.req.valid := s2_valid_masked && !s2_hit && (isPrefetch(s2_req.cmd) || isRead(s2_req.cmd) || isWrite(s2_req.cmd))
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mshr.io.req.bits := s2_req
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mshr.io.req.bits.tag_match := s2_tag_match
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mshr.io.req.bits.old_meta.state := s2_repl_state
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mshr.io.req.bits.old_meta.tag := s2_repl_tag
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mshr.io.req.bits.old_meta := s2_repl_meta
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mshr.io.req.bits.way_en := Mux(s2_tag_match, s2_tag_match_way, s2_replaced_way_en)
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mshr.io.req.bits.data := s2_req.data
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@ -895,12 +922,12 @@ class HellaCache(implicit conf: DCacheConfig) extends Component {
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when (mshr.io.req.fire()) { replacer.miss }
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// replays
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readArb.io.in(0).valid := mshr.io.replay.valid
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readArb.io.in(0).bits := mshr.io.replay.bits
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readArb.io.in(0).bits.way_en := Fix(-1)
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mshr.io.replay.ready := Bool(true)
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s1_replay := mshr.io.replay.fire()
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metaReadArb.io.in(0) <> mshr.io.meta_read
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readArb.io.in(1).valid := mshr.io.replay.valid
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readArb.io.in(1).bits := mshr.io.replay.bits
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readArb.io.in(1).bits.way_en := Fix(-1)
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mshr.io.replay.ready := readArb.io.in(1).ready
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s1_replay := mshr.io.replay.valid && readArb.io.in(1).ready
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metaReadArb.io.in(1) <> mshr.io.meta_read
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metaWriteArb.io.in(0) <> mshr.io.meta_write
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// probes
|
||||
@ -910,7 +937,7 @@ class HellaCache(implicit conf: DCacheConfig) extends Component {
|
||||
prober.io.wb_req <> wb.io.probe
|
||||
prober.io.way_en := s2_tag_match_way
|
||||
prober.io.line_state := s2_hit_state
|
||||
prober.io.meta_read <> metaReadArb.io.in(1)
|
||||
prober.io.meta_read <> metaReadArb.io.in(2)
|
||||
prober.io.meta_write <> metaWriteArb.io.in(1)
|
||||
|
||||
// refills
|
||||
@ -923,9 +950,9 @@ class HellaCache(implicit conf: DCacheConfig) extends Component {
|
||||
|
||||
// writebacks
|
||||
wb.io.req <> mshr.io.wb_req
|
||||
wb.io.meta_read <> metaReadArb.io.in(2)
|
||||
wb.io.data_req <> readArb.io.in(1)
|
||||
wb.io.data_resp := data_resp_mux
|
||||
wb.io.meta_read <> metaReadArb.io.in(3)
|
||||
wb.io.data_req <> readArb.io.in(2)
|
||||
wb.io.data_resp := s2_data_corrected
|
||||
wb.io.probe_rep_data <> io.mem.probe_rep_data
|
||||
|
||||
// store->load bypassing
|
||||
@ -947,9 +974,7 @@ class HellaCache(implicit conf: DCacheConfig) extends Component {
|
||||
}
|
||||
|
||||
// load data subword mux/sign extension
|
||||
val s2_data_word_prebypass =
|
||||
if (conf.isNarrowRead) data_resp_mux(conf.databits-1,0)
|
||||
else data_resp_mux >> Cat(s2_req.addr(log2Up(MEM_DATA_BITS/8)-1,3), Bits(0,log2Up(conf.databits)))
|
||||
val s2_data_word_prebypass = s2_data_uncorrected >> Cat(s2_word_idx, Bits(0,log2Up(conf.databits)))
|
||||
val s2_data_word = Mux(s2_store_bypass, s2_store_bypass_data, s2_data_word_prebypass)
|
||||
val loadgen = new LoadGen(s2_req.typ, s2_req.addr, s2_data_word)
|
||||
|
||||
@ -968,6 +993,11 @@ class HellaCache(implicit conf: DCacheConfig) extends Component {
|
||||
val s2_nack = s2_nack_hit || s2_nack_victim || s2_nack_miss || s2_nack_fence
|
||||
s2_valid_masked := s2_valid && !s2_nack
|
||||
|
||||
val s2_recycle_ecc = (s2_valid || s2_replay) && s2_hit && s2_data_correctable
|
||||
val s2_recycle_next = Reg(resetVal = Bool(false))
|
||||
when (s1_valid || s1_replay) { s2_recycle_next := (s1_valid || s1_replay) && s2_recycle_ecc }
|
||||
s2_recycle := s2_recycle_ecc || s2_recycle_next
|
||||
|
||||
// after a nack, block until nack condition resolves to save energy
|
||||
val block_fence = Reg(resetVal = Bool(false))
|
||||
block_fence := (s2_valid && s2_req.cmd === M_FENCE || block_fence) && !mshr.io.fence_rdy
|
||||
@ -978,7 +1008,7 @@ class HellaCache(implicit conf: DCacheConfig) extends Component {
|
||||
}
|
||||
|
||||
val s2_read = isRead(s2_req.cmd)
|
||||
io.cpu.resp.valid := s2_read && (s2_replay || s2_valid_masked && s2_hit)
|
||||
io.cpu.resp.valid := s2_read && (s2_replay || s2_valid_masked && s2_hit) && !s2_data_correctable
|
||||
io.cpu.resp.bits.nack := s2_valid && s2_nack
|
||||
io.cpu.resp.bits := s2_req
|
||||
io.cpu.resp.bits.replay := s2_replay && s2_read
|
||||
|
||||
@ -17,6 +17,11 @@ object AVec
|
||||
def apply[T <: Data](elts: Seq[T]): Vec[T] = Vec(elts) { elts.head.clone }
|
||||
def apply[T <: Data](elts: Vec[T]): Vec[T] = apply(elts.toSeq)
|
||||
def apply[T <: Data](elt0: T, elts: T*): Vec[T] = apply(elt0 :: elts.toList)
|
||||
|
||||
def tabulate[T <: Data](n: Int)(f: Int => T): Vec[T] =
|
||||
apply((0 until n).map(i => f(i)))
|
||||
def tabulate[T <: Data](n1: Int, n2: Int)(f: (Int, Int) => T): Vec[Vec[T]] =
|
||||
tabulate(n1)(i1 => tabulate(n2)(f(i1, _)))
|
||||
}
|
||||
|
||||
// a counter that clock gates most of its MSBs using the LSB carry-out
|
||||
|
||||
Loading…
Reference in New Issue
Block a user