Generate D$ replay_next signals correctly
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@ -44,6 +44,9 @@ class HellaCacheArbiter(n: Int)(implicit conf: RocketConfiguration) extends Modu
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resp.bits.tag := io.mem.resp.bits.tag >> UInt(log2Up(n))
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resp.bits.nack := io.mem.resp.bits.nack && tag_hit
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resp.bits.replay := io.mem.resp.bits.replay && tag_hit
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resp.bits.load_replay_next := io.mem.resp.bits.load_replay_next && tag_hit
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io.requestor(i).replay_next.valid := io.mem.replay_next.valid &&
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io.mem.replay_next.bits(log2Up(n)-1,0) === UInt(log2Up(n))
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io.requestor(i).replay_next.bits := io.mem.replay_next.bits >> UInt(log2Up(n))
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}
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}
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@ -538,7 +538,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
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(mem_reg_mem_val && io.dmem.xcpt.pf.ld, UInt(10)),
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(mem_reg_mem_val && io.dmem.xcpt.pf.st, UInt(11))))
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val dcache_kill_mem = mem_reg_wen && io.dmem.resp.bits.load_replay_next // structural hazard on writeback port
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val dcache_kill_mem = mem_reg_wen && io.dmem.replay_next.valid // structural hazard on writeback port
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val fpu_kill_mem = mem_reg_fp_val && io.fpu.nack_mem
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val replay_mem = dcache_kill_mem || mem_reg_replay || fpu_kill_mem
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val killm_common = dcache_kill_mem || take_pc_wb || mem_reg_xcpt || !mem_reg_valid
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@ -697,7 +697,6 @@ class HellaCacheReq(implicit val conf: DCacheConfig) extends DCacheBundle {
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class HellaCacheResp(implicit val conf: DCacheConfig) extends DCacheBundle {
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val nack = Bool() // comes 2 cycles after req.fire
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val replay = Bool()
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val load_replay_next = Bool() // next cycle, replay and has_data will be true
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val typ = Bits(width = 3)
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val has_data = Bool()
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val data = Bits(width = conf.databits)
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@ -722,6 +721,7 @@ class HellaCacheExceptions extends Bundle {
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class HellaCacheIO(implicit conf: DCacheConfig) extends Bundle {
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val req = Decoupled(new HellaCacheReq)
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val resp = Valid(new HellaCacheResp).flip
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val replay_next = Valid(Bits(width = conf.reqtagbits)).flip
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val xcpt = (new HellaCacheExceptions).asInput
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val ptw = (new TLBPTWIO).flip
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val ordered = Bool(INPUT)
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@ -1034,13 +1034,15 @@ class HellaCache(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends
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io.cpu.resp.bits.nack := s2_valid && s2_nack
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io.cpu.resp.bits := s2_req
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io.cpu.resp.bits.has_data := isRead(s2_req.cmd) || s2_sc
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io.cpu.resp.bits.load_replay_next := s1_replay && (s1_read || s1_sc)
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io.cpu.resp.bits.replay := s2_replay
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io.cpu.resp.bits.data := loadgen.word
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io.cpu.resp.bits.data_subword := loadgen.byte | s2_sc_fail
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io.cpu.resp.bits.store_data := s2_req.data
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io.cpu.ordered := mshrs.io.fence_rdy && !s1_valid && !s2_valid
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io.cpu.replay_next.valid := s1_replay && (s1_read || s1_sc)
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io.cpu.replay_next.bits := s1_req.tag
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io.mem.grant_ack <> mshrs.io.mem_finish
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}
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