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143 Commits

Author SHA1 Message Date
Megan Wachs 9ba47b76c6 MockAON: Accept the non-debug interrupt as an input to overall reset. 2017-04-07 16:42:32 -07:00
Megan Wachs dbd16e305d Merge pull request #6 from sifive/debug_v013 
Debug v013
 2017-03-31 15:14:35 -07:00
Megan Wachs 70ac4044d1 spi: correct polarity of FIRRTL combo loop detection workaround. 2017-03-31 13:49:34 -07:00
Megan Wachs 1af6ce1c85 Merge remote-tracking branch 'origin/fix-false-comb-loop' into HEAD 2017-03-30 20:01:30 -07:00
Jack Koenig 6a3b5e1a31 "Fix" false combinational loop through SPIArbiter 
Mux1H converts aggregates to UInt, muxes, then converts back which can
look like a cominational loop.
 2017-03-30 19:12:15 -07:00
Megan Wachs 3f6f10f4ed Merge remote-tracking branch 'origin/master' into debug-0.13 2017-03-27 18:48:24 -07:00
Yunsup Lee 3c2277447d rename l2FrontendBus as fsb 2017-03-25 19:51:53 -07:00
Yunsup Lee e2073feef8 rename l2FrontendBus as fsb 2017-03-24 21:38:31 -07:00
Megan Wachs faeb14dc5a JTAG: make TRSTn optional for all helpers as well to match the IO. 2017-03-24 17:27:55 -07:00
Megan Wachs 2c47cc4abd Merge remote-tracking branch 'origin/master' into debug-0.13 2017-03-22 19:16:20 -07:00
Yunsup Lee c1872c574b update TLRegisterNode to take Seq of AddressSet 2017-03-21 22:12:37 -07:00
Megan Wachs c6d7326669 TLSPI: address parameter must now be a sequence. 2017-03-21 17:51:33 -07:00
Megan Wachs 77246eaada Adjust JTAG for rocket-chip changes 2017-03-14 14:52:39 -07:00
Megan Wachs 25356957fe Merge remote-tracking branch 'origin/master' into debug-0.13 2017-03-10 14:09:24 -08:00
Wesley W. Terpstra 062203ae18 xilinx pcie: add the high PCIe address bits (physical path) 
The format is taken from here:
http://lxr.free-electrons.com/source/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
 2017-03-02 21:22:41 -08:00
Wesley W. Terpstra 64bff44462 Merge pull request #4 from sifive/periphery-keys 
DTS
 2017-03-02 21:00:44 -08:00
Wesley W. Terpstra 46aa6b0ac4 devices: include DTS meta-data 2017-03-02 20:39:30 -08:00
Wesley W. Terpstra baccd5ada2 devices: create periphery keys for all devices 
Standardize how they are connected to the periphery bus
 2017-03-02 20:39:25 -08:00
Megan Wachs bf9b81f2bc jtag: The jtag interfaces have moved to a different package. 2017-03-02 14:46:34 -08:00
Megan Wachs 072d0c1b58 Merge pull request #2 from sifive/homogenous_bag_peripherals 
Use HeterogenousBag to handle lists of peripherals
 2017-02-16 18:45:48 -08:00
Megan Wachs 03be9aba67 Use HomogenousBag to handle lists of peripherals 
Previously we had to do weird things to make non-homogenous
lists of items (e.g. PWM Peripherals where ncmp were different from one to
the other) into a vector. But now Chisel supports a Record type,
and we use the HomogenousBag utility to do this more naturally.
This also deletes all the cruft which was introduced to get
around the limitation which doesn't exist anymore.
 2017-02-16 17:52:24 -08:00
solomatnikov 348bbb97f4 Merge pull request #1 from sifive/i2c 
I2c implementation
 2017-02-10 14:30:01 -08:00
Alex Solomatnikov a915e84a9e Merge remote-tracking branch 'origin/master' into i2c 2017-02-09 18:45:35 -08:00
Alex Solomatnikov 095cb158dd Flipped polarity of output enables to match Guava pins logic 2017-02-09 11:37:40 -08:00
Alex Solomatnikov 72e4b60d81 Made regs 32-bit word aligned to match the rest of the system 2017-02-09 11:36:19 -08:00
Alex Solomatnikov 9ca71c0cf2 Added note: WISHBONE interface replaced by Tilelink2 2017-02-07 16:14:28 -08:00
Alex Solomatnikov c311b6ec63 Added license 2017-02-07 15:58:04 -08:00
Alex Solomatnikov 5a0d084b38 Renamed i2cDevices to i2c 2017-02-06 10:39:47 -08:00
Wesley W. Terpstra 88e4c8ee20 xilinx mig: track changes in rocket-chip 2017-02-03 18:17:58 -08:00
Alex Solomatnikov d474b5ceb2 Addressing comments: bool style, comments, removed suggestName 2017-02-03 18:10:03 -08:00
Alex Solomatnikov 3781d1fb1a Bug fixes: passing OC WB test 2017-02-03 16:41:59 -08:00
Wesley W. Terpstra c010a1557a sifive-blocks: trust diplomacy to get names right 2017-02-01 13:53:54 -08:00
Alex Solomatnikov 2cc1012fa2 Completed Chisel RTL (not tested yet) 2017-01-31 17:20:53 -08:00
Wesley W. Terpstra 535be3e976 spi: work around ucb-bar/chisel3#472 2017-01-31 14:03:14 -08:00
Wesley W. Terpstra 5b6760394d xilinx ip: adjust to new diplomacy API 2017-01-30 11:33:30 -08:00
Alex Solomatnikov 9d2a173b15 Initial (compilable) version of I2C (no actual logic yet) 2017-01-24 14:58:01 -08:00
Wesley W. Terpstra d61d86e084 xilinx pcie: put buffers before the outputs to the controller 2017-01-20 22:38:27 -08:00
Wesley W. Terpstra c68e44ec55 mig: track change to Blind port API in rocket 2017-01-19 19:53:03 -08:00
Wesley W. Terpstra 45c491cd69 LazyModule: provide Parameters 
This tracks PR #478 in rocketchip.
 2016-12-07 13:21:20 -08:00
Wesley W. Terpstra 1443834186 xilinx pcie: bytes, not bits 
This bug amazingly compiled correctly and ran correctly!

It was saved by the AXIFragmenter which turned the "narrow burst" into
individual beats that then got converted to 64b in TileLink land via
inspection of the mask bits.

The consequence is that AXI bus mastering proceeded at one word per
DDR round-trip. Now it is one cache line per DDR round-trip. When we
get L2 back in the design, it should really fly!
 2016-12-06 16:13:12 -08:00
Wesley W. Terpstra ca7555bd4d RegMapFIFO: amoor.w can do thread-safe TX 2016-12-02 17:48:17 -08:00
Richard Xia b8ecb7853b Add /target to .gitignore. 2016-11-30 13:29:54 -08:00
SiFive 7916ef5249 Initial commit. 2016-11-29 04:08:44 -08:00