riscv/sifive-blocks
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Freedom RTL blocks (https://github.com/sifive/sifive-blocks)
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Scala 99.8%
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Megan Wachs dbd16e305d Merge pull request #6 from sifive/debug_v013 
Debug v013
2017-03-31 15:14:35 -07:00
src/main/scala spi: correct polarity of FIRRTL combo loop detection workaround. 2017-03-31 13:49:34 -07:00
vsrc Initial commit. 2016-11-29 04:08:44 -08:00
.gitignore Add /target to .gitignore. 2016-11-30 13:29:54 -08:00
LICENSE Initial commit. 2016-11-29 04:08:44 -08:00