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devices: include DTS meta-data

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This commit is contained in:
Wesley W. Terpstra
2017-03-02 20:28:38 -08:00
committed by Henry Cook
parent baccd5ada2
commit 46aa6b0ac4
9 changed files with 42 additions and 11 deletions
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2
src/main/scala/devices/gpio/GPIO.scala
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@@ -286,6 +286,6 @@ object GPIOInputPinCtrl {
// Magic TL2 Incantation to create a TL2 Slave
class TLGPIO(w: Int, c: GPIOParams)(implicit p: Parameters)
extends TLRegisterRouter(c.address, interrupts = c.width, beatBytes = w)(
extends TLRegisterRouter(c.address, "gpio", Seq("sifive,gpio0"), interrupts = c.width, beatBytes = w)(
new TLRegBundle(c, _) with HasGPIOBundleContents)(
new TLRegModule(c, _, _) with HasGPIOModuleContents)

2
src/main/scala/devices/i2c/I2C.scala
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@@ -535,6 +535,6 @@ trait HasI2CModuleContents extends Module with HasRegMap {
// Magic TL2 Incantation to create a TL2 Slave
class TLI2C(w: Int, c: I2CParams)(implicit p: Parameters)
extends TLRegisterRouter(c.address, interrupts = 1, beatBytes = w)(
extends TLRegisterRouter(c.address, "i2c", Seq("sifive,i2c0"), interrupts = 1, beatBytes = w)(
new TLRegBundle(c, _) with HasI2CBundleContents)(
new TLRegModule(c, _, _) with HasI2CModuleContents)

2
src/main/scala/devices/mockaon/MockAON.scala
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@@ -95,6 +95,6 @@ trait HasMockAONModuleContents extends Module with HasRegMap {
}
class TLMockAON(w: Int, c: MockAONParams)(implicit p: Parameters)
extends TLRegisterRouter(c.address, interrupts = 2, size = c.size, beatBytes = w, concurrency = 1)(
extends TLRegisterRouter(c.address, "aon", Seq("sifive,aon0"), interrupts = 2, size = c.size, beatBytes = w, concurrency = 1)(
new TLRegBundle(c, _) with HasMockAONBundleContents)(
new TLRegModule(c, _, _) with HasMockAONModuleContents)

2
src/main/scala/devices/pwm/PWM.scala
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@@ -62,6 +62,6 @@ trait HasPWMModuleContents extends Module with HasRegMap {
}
class TLPWM(w: Int, c: PWMParams)(implicit p: Parameters)
extends TLRegisterRouter(c.address, interrupts = c.ncmp, size = c.size, beatBytes = w)(
extends TLRegisterRouter(c.address, "pwm", Seq("sifive,pwm0"), interrupts = c.ncmp, size = c.size, beatBytes = w)(
new TLRegBundle(c, _) with HasPWMBundleContents)(
new TLRegModule(c, _, _) with HasPWMModuleContents)

5
src/main/scala/devices/spi/TLSPI.scala
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@@ -109,8 +109,9 @@ class SPITopModule[B <: SPITopBundle](c: SPIParamsBase, bundle: => B, outer: TLS
abstract class TLSPIBase(w: Int, c: SPIParamsBase)(implicit p: Parameters) extends LazyModule {
require(isPow2(c.rSize))
val rnode = TLRegisterNode(address = AddressSet(c.rAddress, c.rSize-1), beatBytes = w)
val intnode = IntSourceNode(1)
val device = new SimpleDevice("spi", Seq("sifive,spi0"))
val rnode = TLRegisterNode(address = AddressSet(c.rAddress, c.rSize-1), device = device, beatBytes = w)
val intnode = IntSourceNode(IntSourcePortSimple(resources = device.int))
}
class TLSPI(w: Int, c: SPIParams)(implicit p: Parameters) extends TLSPIBase(w,c)(p) {

2
src/main/scala/devices/uart/UART.scala
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@@ -260,6 +260,6 @@ trait HasUARTTopModuleContents extends Module with HasUARTParameters with HasReg
// Magic TL2 Incantation to create a TL2 UART
class TLUART(w: Int, c: UARTParams)(implicit p: Parameters)
extends TLRegisterRouter(c.address, interrupts = 1, beatBytes = w)(
extends TLRegisterRouter(c.address, "serial", Seq("sifive,uart0"), interrupts = 1, beatBytes = w)(
new TLRegBundle(c, _) with HasUARTTopBundleContents)(
new TLRegModule(c, _, _) with HasUARTTopModuleContents)

2
src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
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@@ -26,10 +26,12 @@ class XilinxVC707MIGIO extends Bundle with VC707MIGUnidirectionalIODDR
}
class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC707MIGParameters {
val device = new MemoryDevice
val node = TLInputNode()
val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters(
address = Seq(AddressSet(p(ExtMem).base, p(ExtMem).size-1)),
resources = device.reg,
regionType = RegionType.UNCACHED,
executable = true,
supportsWrite = TransferSizes(1, 256*8),

4
src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
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@@ -23,12 +23,13 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
val slave = TLInputNode()
val control = TLInputNode()
val master = TLOutputNode()
val intnode = IntSourceNode(1)
val intnode = IntOutputNode()
val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1)
axi_to_pcie_x1.slave := AXI4Buffer()(TLToAXI4(idBits=4)(slave))
axi_to_pcie_x1.control := AXI4Buffer()(AXI4Fragmenter(lite=true, maxInFlight=4)(TLToAXI4(idBits=0)(control)))
master := TLWidthWidget(8)(AXI4ToTL()(AXI4Fragmenter()(axi_to_pcie_x1.master)))
intnode := axi_to_pcie_x1.intnode
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
@@ -40,7 +41,6 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
}
io.port <> axi_to_pcie_x1.module.io.port
io.interrupt(0)(0) := axi_to_pcie_x1.module.io.interrupt_out
//PCIe Reference Clock
val ibufds_gte2 = Module(new IBUFDS_GTE2)

32
src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
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@@ -5,6 +5,7 @@ import Chisel._
import config._
import diplomacy._
import uncore.axi4._
import uncore.tilelink2.{IntSourceNode, IntSourcePortSimple}
import junctions._
// IP VLNV: xilinx.com:customize_ip:vc707pcietoaxi:1.0
@@ -167,9 +168,33 @@ class vc707axi_to_pcie_x1() extends BlackBox
class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
{
val device = new SimpleDevice("pci", Seq("xlnx,axi-pcie-host-1.00.a")) {
override def describe(resources: ResourceBindings): Description = {
val Description(name, mapping) = super.describe(resources)
val intc = "pcie_intc"
def ofInt(x: Int) = Seq(ResourceInt(BigInt(x)))
def ofMap(x: Int) = Seq(0, 0, 0, x).flatMap(ofInt) ++ Seq(ResourceReference(intc)) ++ ofInt(x)
val extra = Map(
"#address-cells" -> ofInt(3),
"#size-cells" -> ofInt(2),
"#interrupt-cells" -> ofInt(1),
"device_type" -> Seq(ResourceString("pci")),
"interrupt-map-mask" -> Seq(0, 0, 0, 7).flatMap(ofInt),
"interrupt-map" -> Seq(1, 2, 3, 4).flatMap(ofMap),
"ranges" -> resources("ranges").map { case Binding(_, ResourceAddress(address, _, _, _)) =>
ResourceMapping(address, 0) },
"interrupt-controller" -> Seq(ResourceMap(labels = Seq(intc), value = Map(
"interrupt-controller" -> Nil,
"#address-cells" -> ofInt(0),
"#interrupt-cells" -> ofInt(1)))))
Description(name, mapping ++ extra)
}
}
val slave = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters(
address = List(AddressSet(0x60000000L, 0x1fffffffL)),
resources = Seq(Resource(device, "ranges")),
executable = true,
supportsWrite = TransferSizes(1, 256),
supportsRead = TransferSizes(1, 256),
@@ -179,6 +204,7 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
val control = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters(
address = List(AddressSet(0x50000000L, 0x03ffffffL)),
resources = device.reg,
supportsWrite = TransferSizes(1, 4),
supportsRead = TransferSizes(1, 4),
interleavedId = Some(0))), // no read interleaving b/c AXI-lite
@@ -189,6 +215,8 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
id = IdRange(0, 1),
aligned = false)))))
val intnode = IntSourceNode(IntSourcePortSimple(resources = device.int))
lazy val module = new LazyModuleImp(this) {
// The master on the control port must be AXI-lite
require (control.edgesIn(0).master.endId == 1)
@@ -204,7 +232,7 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
val control_in = control.bundleIn
val master_out = master.bundleOut
val REFCLK = Bool(INPUT)
val interrupt_out = Bool(OUTPUT)
val interrupt_out = intnode.bundleOut
}
val blackbox = Module(new vc707axi_to_pcie_x1)
@@ -222,7 +250,7 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
io.port.pci_exp_txn := blackbox.io.pci_exp_txn
blackbox.io.pci_exp_rxp := io.port.pci_exp_rxp
blackbox.io.pci_exp_rxn := io.port.pci_exp_rxn
io.interrupt_out := blackbox.io.interrupt_out
io.interrupt_out(0)(0) := blackbox.io.interrupt_out
blackbox.io.REFCLK := io.REFCLK
//s