riscv/sifive-blocks
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  • 88f1cbe420 Use NonBlockingEnqueue for terminal writes ml507 Klemens Schölhorn 2018-05-14 20:05:14 +0200
  • 48d8524c4a Move terminal into own clock domain using AsyncQueue Klemens Schölhorn 2018-04-30 22:50:39 +0200
  • d7b9834d96 Add TLTerminal (write-only terminal TL slave) Klemens Schölhorn 2018-04-30 00:45:27 +0200
  • 7ac56c01af
         Merge pull request #53 from sifive/chiplink Wesley W. Terpstra 2018-03-22 16:18:30 -0700
  • ac55313e8e msi: add a MSIMaster to bridge interrupts over ChipLink Wesley W. Terpstra 2018-03-22 15:57:47 -0700
  • 3db375ef43 devices: add support for the chiplink protocol Wesley W. Terpstra 2018-03-22 14:29:36 -0700
  • 48a9acc8a4
         Merge pull request #52 from sifive/spi_sync Megan Wachs 2018-03-07 14:45:44 -0800
  • fb4977b518 SPI: Use the standard synchronizer primitive for the SPI DQ inputs Megan Wachs 2018-03-07 09:54:56 -0800
  • 6795f40107 spi: SPIParamsBase param needs to be public Henry Cook 2018-03-04 13:26:19 -0800
  • 39287b9215 Remove cloneTypes in favor of autoclonetype (#51) Jack Koenig 2018-03-04 10:29:51 -0800
  • 00fbfb6dd8
         periphery: bus api update (#50) Henry Cook 2018-03-01 01:15:02 -0800
  • 3dee152775
         Bug fix: arbLost should be asserted when bitState =/= s_bit_idle (#49) solomatnikov 2018-02-23 12:09:18 -0800
  • 462976a070
         Merge pull request #48 from sifive/i2c_int solomatnikov 2018-02-22 18:48:09 -0800
  • ef8139f18c Do not allow status read if status.transferInProgress is going to change next cycle Alex Solomatnikov 2018-02-22 18:43:39 -0800
  • 6c5b80671c i2c: Allow irq to be cleared Megan Wachs 2018-02-16 15:49:09 -0800
  • 14ffd35f5c uart: Eliminate systemic baud rate error with low divisor values Albert Ou 2018-01-04 19:51:24 -0800
  • 9052a079d4
         Merge pull request #46 from sifive/gpio_iof_pueds Megan Wachs 2017-11-08 17:18:02 -0800
  • 90404980b8 GPIO: IOF should not override PUE and DS Megan Wachs 2017-11-08 15:15:32 -0800
  • d1d2f47f60
         PMU: adapt to new chisel API (#45) Wesley W. Terpstra 2017-11-02 15:44:02 -0700
  • 90e6ea1d2d
         devices: switch to using node-style API (#44) Wesley W. Terpstra 2017-10-28 12:29:31 -0700
  • e4960a4e5a sifive-blocks: update to new rocket API (#43) Wesley W. Terpstra 2017-10-26 16:10:18 -0700
  • e6da80733e Merge pull request #42 from sifive/enhanced_to_base_pin Megan Wachs 2017-10-11 06:43:41 -0700
  • 94f8c1705d pinctrl: Add the ability to convert EnhancedPin to BasePin Megan Wachs 2017-10-06 13:43:23 -0700
  • e2695500cd Merge pull request #41 from sifive/pwm_invert Megan Wachs 2017-10-05 16:32:26 -0700
  • 3e47ed6b33 PWM: Add the ability to invert the output directly in PWM (without GPIO pinmux) Megan Wachs 2017-10-02 11:13:33 -0700
  • 4fcf349adb diplomacy: update to new API (#40) Wesley W. Terpstra 2017-09-27 16:33:18 -0700
  • fe65a87c5c Merge pull request #39 from sifive/signal_bundles Megan Wachs 2017-09-25 11:21:08 -0700
  • 77df75f4ed GPIO Pins needs clone type. Megan Wachs 2017-09-22 16:38:37 -0700
  • 5d1e9b793a signal_bundles: add missing file Megan Wachs 2017-09-22 13:55:55 -0700
  • 81e301f9f7 pinctrl: Create extendable Signal classes Megan Wachs 2017-09-22 13:17:31 -0700
  • 38f537c438 device pins: Create classes that can be something other than a Pin subclass Megan Wachs 2017-09-20 16:43:42 -0700
  • 6a13639cf3 SPI: Make it easier to build arbitrary bundles Megan Wachs 2017-09-20 16:21:21 -0700
  • f8dcfbacfa uart: use PeripheryBusKey (#38) Henry Cook 2017-09-15 14:54:10 -0700
  • d5554bfe95 Merge pull request #37 from sifive/synchronizers Megan Wachs 2017-09-07 13:34:14 -0700
  • 97c3fcb4b6 shiftregs: Use SyncResetSynchronizerShiftReg primitives where appropriate Megan Wachs 2017-09-06 10:59:07 -0700
  • 4381e395af i2c/uart: Name the synchronizers Megan Wachs 2017-09-05 18:40:22 -0700
  • 48222bcd2d gpio: Use Synchronizer for the inputs Megan Wachs 2017-09-05 18:35:09 -0700
  • 1feaefe4c5 i2c, uart: Use Synchronizer primitives for the inputs Megan Wachs 2017-09-05 18:32:37 -0700
  • c68d556768 ShiftRegInit: use the rocket-chip version since it is there now Megan Wachs 2017-09-05 17:51:40 -0700
  • 7d07e3af0b regs: remove duplicate ShiftReg file which is now in rocket-chip Megan Wachs 2017-09-05 17:33:32 -0700
  • acb8889382 remove duplicate ResetCatchAndSync definition Megan Wachs 2017-08-24 18:12:36 -0700
  • 402017d34e Merge pull request #35 from sifive/spi-buffers Megan Wachs 2017-08-20 16:47:01 -0700
  • 70c25846b8 spi: Make memory mapped interface depth a parameter Megan Wachs 2017-08-20 12:39:38 -0700
  • a814cba04f spi: put a request buffer infront of SPI Wesley W. Terpstra 2017-08-19 12:36:28 -0700
  • f266b55da9 Merge pull request #34 from ss2783/master Shreesha Srinath 2017-08-18 14:27:57 -0700
  • 249c23e617 Renamed ShiftReg to ShiftRegister Shreesha Srinath 2017-08-17 18:22:51 -0700
  • 7035ccc431 Updates to go with the fpga-shells directory Shreesha Srinath 2017-08-17 18:11:07 -0700
  • d973c659eb uart: make it easy to simulate large text printouts (#33) Wesley W. Terpstra 2017-08-10 16:32:48 -0700
  • 5b74df20a1 Merge pull request #31 from ss2783/fix-mockaon Shreesha Srinath 2017-08-04 11:46:06 -0700
  • 26dd0af657 mockaon: Adds logic to detect external rtc toggles Shreesha Srinath 2017-08-02 18:11:05 -0700
  • 7f368987a8 Merge pull request #30 from sifive/spi Albert Ou 2017-08-02 13:33:11 -0900
  • c59356d1de spi: Fix invalid D channel response when flash interface is disabled Albert Ou 2017-08-02 13:50:00 -0700
  • 015f87ec6b allow bundle content params to be specified via a def (#29) Henry Cook 2017-08-02 11:46:27 -0700
  • fced2323bd spi: remove removed sink arg Wesley W. Terpstra 2017-07-26 16:02:44 -0700
  • 86010395ad Merge pull request #27 from sifive/typed_pad_ctrl Yunsup Lee 2017-07-25 16:37:46 -0700
  • 4cb2f8af17 mockaon: rename pads to pins Yunsup Lee 2017-07-25 15:02:22 -0700
  • aa6d911c26 Ports: Rename the 'fromXYZPort' to 'fromPort' since it's redundant Megan Wachs 2017-07-25 08:36:28 -0700
  • 2139ab0d98 Merge remote-tracking branch 'origin/master' into typed_pad_ctrl Megan Wachs 2017-07-25 07:05:22 -0700
  • 5e51e1e931 uart: use PeripheryBusParams.frequency to calculate default divisor (#28) Yunsup Lee 2017-07-25 00:56:22 -0700
  • 0a80d1987d Merge remote-tracking branch 'origin/master' into typed_pad_ctrl Megan Wachs 2017-07-24 09:17:53 -0700
  • 9ae6413273 periphery: peripherals now in coreplex (#26) Henry Cook 2017-07-23 08:31:44 -0700
  • 2bad829e6e gpio: Add missing file Megan Wachs 2017-07-20 14:53:34 -0700
  • 06f0d20742 Add missing cloneType methods to pin bundles Megan Wachs 2017-07-20 11:36:31 -0700
  • 00086c26e6 i2c: Remove pluralization on the bundle name, i2c not i2cs Megan Wachs 2017-07-20 10:53:44 -0700
  • ef4f2ed888 Remove pluralization on interface names. Require clocks and resets explicitly when necessary Megan Wachs 2017-07-19 14:51:50 -0700
  • 4d74e8f67f Make it possible to adjust the type of pad controls used, and seperate out some of the "GPIO Peripheral" from "Pin Control" Megan Wachs 2017-07-18 10:58:04 -0700
  • fb9dd31374 Refactor package hierarchy. (#25) Henry Cook 2017-07-07 10:48:57 -0700
  • 66b2fd11bd vc707 axi enhancements (#24) Wesley W. Terpstra 2017-06-30 12:36:33 -0700
  • 886680af49 mig: fix MemoryDevice to use 'reg' properly Wesley W. Terpstra 2017-06-29 13:41:30 -0700
  • a8e20f447c spi: include mem region (#23) Wesley W. Terpstra 2017-06-28 17:46:45 -0700
  • 3d8c502fce diplomacy: add reg-names to devices (#22) Wesley W. Terpstra 2017-06-28 17:45:18 -0700
  • 2154e9eb3f gpio: Make IOF optional (#21) Megan Wachs 2017-06-19 12:41:38 -0700
  • 473464eaa9 make some base bundle classes easier to clone (#20) Henry Cook 2017-06-14 19:47:56 -0700
  • 90d3931f5a spi: add dts ranges field for memory mapped spi (#19) Wesley W. Terpstra 2017-06-14 17:06:55 -0700
  • dacca7e7b1 Merge pull request #18 from sifive/lazy-raw-module-imp Henry Cook 2017-06-13 15:52:11 -0700
  • 8bfda68858 More Peripheral-to-pins cleanups Megan Wachs 2017-06-13 11:00:29 -0700
  • b3f656affe UART: actually return the pins, not just the module. We should do this for the other peripherals as well Megan Wachs 2017-06-12 18:08:35 -0700
  • b06b80dccd GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they are more useful. Megan Wachs 2017-06-12 17:53:51 -0700
  • 7c118790cb GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they are more useful. Megan Wachs 2017-06-12 17:53:08 -0700
  • d4bb8a77ea periphery: convert periphery bundle traits to work with system-level multi-io module Henry Cook 2017-06-05 14:33:53 -0700
  • 27b00e177c Merge pull request #17 from sifive/peripheral_options Megan Wachs 2017-06-09 22:07:43 -0700
  • 79f64de12c peripheral_options: Actually compiles Megan Wachs 2017-06-09 13:53:22 -0700
  • 29226701a8 SPIFlash: make it listable Megan Wachs 2017-06-08 16:29:01 -0700
  • c89f163c0d GPIO: Make GPIO peripheral another listable one Megan Wachs 2017-06-08 16:25:20 -0700
  • 0ca609d324 vc707axi: track rocketchip API changes (#16) Wesley W. Terpstra 2017-06-02 15:56:18 -0700
  • 0f8722f80c uart: power-on with the right divider for the design (#15) Wesley W. Terpstra 2017-05-13 23:38:20 -0700
  • 9c8fe44670 Merge pull request #14 from sifive/async-pcie Wesley W. Terpstra 2017-05-12 23:15:14 -0700
  • c4c158963c vc707mig: use an external ibuf Wesley W. Terpstra 2017-05-12 23:07:10 -0700
  • 0ed21ba465 xilinxvc707pciex1: push to a dedicated clock domain Wesley W. Terpstra 2017-05-12 22:59:48 -0700
  • b3f9607512 xilinx mig: put a buffer infront of the controller (#13) Wesley W. Terpstra 2017-05-11 11:50:07 -0700
  • 178ac84b59 xilinxvc707pciex1: better wrapper for AXI4-Lite control node (#12) Wesley W. Terpstra 2017-05-08 01:08:37 -0700
  • 9cb80ac913 Merge pull request #10 from sifive/axi-mmio Henry Cook 2017-05-03 11:46:30 -0700
  • fd89474621 Merge pull request #11 from sifive/spi Yunsup Lee 2017-05-02 14:36:39 -0700
  • 75d6a7c6ea spi: Fix off-by-one error in calculating cycles per data frame Albert Ou 2017-05-02 12:35:34 -0700
  • eea10f5129 spi: Fix io.port.dq(3) output enable Albert Ou 2017-05-02 12:07:37 -0700
  • a24fa9b444 axi4: switch to new pipelined converters Wesley W. Terpstra 2017-04-26 13:10:50 -0700
  • 6eddf517a3 Merge pull request #9 from sifive/vc707_mig_analog_inout Henry Styles 2017-04-25 10:18:46 -0700
  • b882d6da93 Use _chisel3 analog for MIG inout Henry Styles 2017-04-25 10:15:00 -0700
  • b1dfcfc0b0 Added stall for read after write (#8) solomatnikov 2017-04-25 09:14:00 -0700
  • ebd3ffa57e Merge pull request #7 from sifive/ndreset Megan Wachs 2017-04-10 14:25:08 -0700