Wesley W. Terpstra 062203ae18 xilinx pcie: add the high PCIe address bits (physical path) ...

The format is taken from here:
http://lxr.free-electrons.com/source/Documentation/devicetree/bindings/pci/xilinx-pcie.txt

2017-03-02 21:22:41 -08:00

src/main/scala

xilinx pcie: add the high PCIe address bits (physical path)

2017-03-02 21:22:41 -08:00

vsrc

Initial commit.

2016-11-29 04:08:44 -08:00

.gitignore

Add /target to .gitignore.

2016-11-30 13:29:54 -08:00

LICENSE

Initial commit.

2016-11-29 04:08:44 -08:00

Description

Freedom RTL blocks (https://github.com/sifive/sifive-blocks)

280 KiB

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Scala 99.8%

Verilog 0.2%