riscv/sifive-blocks
1
0
Fork 0
Code Releases Activity
36 Commits 1 Branch 0 Tags
3c2277447dc4d7a60ad68eda7a50d81c280392e6
T
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
Yunsup Lee 3c2277447d rename l2FrontendBus as fsb
2017-03-25 19:51:53 -07:00
src/main/scala
rename l2FrontendBus as fsb
2017-03-25 19:51:53 -07:00
vsrc
Initial commit.
2016-11-29 04:08:44 -08:00
.gitignore
Add /target to .gitignore.
2016-11-30 13:29:54 -08:00
LICENSE
Initial commit.
2016-11-29 04:08:44 -08:00
S
Description
Freedom RTL blocks (https://github.com/sifive/sifive-blocks)
280 KiB
Languages
Scala 99.8%
Verilog 0.2%