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143 Commits

Author SHA1 Message Date
88f1cbe420 Use NonBlockingEnqueue for terminal writes
This provides feedback to the programm if the last value was already
printed to the terminal. If not, new values are ignored (unchanged).
2018-05-14 20:05:14 +02:00
48d8524c4a Move terminal into own clock domain using AsyncQueue 2018-04-30 22:50:39 +02:00
d7b9834d96 Add TLTerminal (write-only terminal TL slave) 2018-04-30 00:45:27 +02:00
7ac56c01af Merge pull request #53 from sifive/chiplink
devices: add support for the chiplink protocol
2018-03-22 16:18:30 -07:00
ac55313e8e msi: add a MSIMaster to bridge interrupts over ChipLink 2018-03-22 16:06:12 -07:00
3db375ef43 devices: add support for the chiplink protocol 2018-03-22 16:06:10 -07:00
48a9acc8a4 Merge pull request #52 from sifive/spi_sync
SPI: Use the standard synchronizer primitive for the SPI DQ inputs
2018-03-07 14:45:44 -08:00
fb4977b518 SPI: Use the standard synchronizer primitive for the SPI DQ inputs 2018-03-07 09:54:56 -08:00
6795f40107 spi: SPIParamsBase param needs to be public 2018-03-04 13:26:19 -08:00
39287b9215 Remove cloneTypes in favor of autoclonetype (#51)
* Remove cloneTypes in favor of autoclonetype

* Consistently use private val for autoclonetype
2018-03-04 10:29:51 -08:00
00fbfb6dd8 periphery: bus api update (#50) 2018-03-01 01:15:02 -08:00
3dee152775 Bug fix: arbLost should be asserted when bitState =/= s_bit_idle (#49) 2018-02-23 12:09:18 -08:00
462976a070 Merge pull request #48 from sifive/i2c_int
i2c interrupt: allow irq to be cleared
2018-02-22 18:48:09 -08:00
ef8139f18c Do not allow status read if status.transferInProgress is going to change next cycle 2018-02-22 18:43:39 -08:00
6c5b80671c i2c: Allow irq to be cleared 2018-02-16 16:34:10 -08:00
14ffd35f5c uart: Eliminate systemic baud rate error with low divisor values
This refactors the receiver logic to compensate for the case of the baud
rate divisor not being multiple of the oversampling period.

Previously, the bit time was effectively rounded to (s * floor(div / s))
cycles, where "s" is the oversampling factor - the number of
intermediate samples for each data bit.  The remainder r = (div % s) was
ignored, thereby resulting in gradually accumulated drift that became
significant for divisor values on the same order of magnitude as "s".

The revised approach inserts the required additional delay by extending
the last "r" samples of a given data bit by one cycle each.
2018-01-04 19:51:24 -08:00
9052a079d4 Merge pull request #46 from sifive/gpio_iof_pueds
GPIO: IOF should not override PUE and DS
2017-11-08 17:18:02 -08:00
90404980b8 GPIO: IOF should not override PUE and DS 2017-11-08 15:15:32 -08:00
d1d2f47f60 PMU: adapt to new chisel API (#45) 2017-11-02 15:44:02 -07:00
90e6ea1d2d devices: switch to using node-style API (#44) 2017-10-28 12:29:31 -07:00
e4960a4e5a sifive-blocks: update to new rocket API (#43) 2017-10-26 16:10:18 -07:00
e6da80733e Merge pull request #42 from sifive/enhanced_to_base_pin
pinctrl: Add the ability to convert EnhancedPin to BasePin
2017-10-11 06:43:41 -07:00
94f8c1705d pinctrl: Add the ability to convert EnhancedPin to BasePin 2017-10-06 13:43:23 -07:00
e2695500cd Merge pull request #41 from sifive/pwm_invert
PWM: Add the ability to invert the output directly in PWM
2017-10-05 16:32:26 -07:00
3e47ed6b33 PWM: Add the ability to invert the output directly in PWM (without GPIO pinmux) 2017-10-02 15:08:06 -07:00
4fcf349adb diplomacy: update to new API (#40) 2017-09-27 16:33:18 -07:00
fe65a87c5c Merge pull request #39 from sifive/signal_bundles
Create Signal Bundles vs just Pins
2017-09-25 11:21:08 -07:00
77df75f4ed GPIO Pins needs clone type. 2017-09-22 16:38:37 -07:00
5d1e9b793a signal_bundles: add missing file 2017-09-22 13:55:55 -07:00
81e301f9f7 pinctrl: Create extendable Signal classes 2017-09-22 13:17:31 -07:00
38f537c438 device pins: Create classes that can be something other than a Pin subclass 2017-09-20 16:43:42 -07:00
6a13639cf3 SPI: Make it easier to build arbitrary bundles 2017-09-20 16:21:21 -07:00
f8dcfbacfa uart: use PeripheryBusKey (#38) 2017-09-15 14:54:10 -07:00
d5554bfe95 Merge pull request #37 from sifive/synchronizers
remove duplicate ResetCatchAndSync definition
2017-09-07 13:34:14 -07:00
97c3fcb4b6 shiftregs: Use SyncResetSynchronizerShiftReg primitives where appropriate 2017-09-06 10:59:07 -07:00
4381e395af i2c/uart: Name the synchronizers 2017-09-05 18:40:22 -07:00
48222bcd2d gpio: Use Synchronizer for the inputs 2017-09-05 18:35:09 -07:00
1feaefe4c5 i2c, uart: Use Synchronizer primitives for the inputs 2017-09-05 18:32:37 -07:00
c68d556768 ShiftRegInit: use the rocket-chip version since it is there now 2017-09-05 17:51:40 -07:00
7d07e3af0b regs: remove duplicate ShiftReg file which is now in rocket-chip 2017-09-05 17:33:32 -07:00
acb8889382 remove duplicate ResetCatchAndSync definition 2017-08-24 18:12:36 -07:00
402017d34e Merge pull request #35 from sifive/spi-buffers
spi: put a request buffer infront of SPI
2017-08-20 16:47:01 -07:00
70c25846b8 spi: Make memory mapped interface depth a parameter 2017-08-20 12:39:38 -07:00
a814cba04f spi: put a request buffer infront of SPI
This will prevent SPI from blocking other pbus requests.
2017-08-19 12:52:10 -07:00
f266b55da9 Merge pull request #34 from ss2783/master
Updates to go with the fpga-shells directory
2017-08-18 14:27:57 -07:00
249c23e617 Renamed ShiftReg to ShiftRegister 2017-08-17 18:22:51 -07:00
7035ccc431 Updates to go with the fpga-shells directory 2017-08-17 18:12:49 -07:00
d973c659eb uart: make it easy to simulate large text printouts (#33) 2017-08-10 16:32:48 -07:00
5b74df20a1 Merge pull request #31 from ss2783/fix-mockaon
mockaon: Adds logic to detect external rtc toggles
2017-08-04 11:46:06 -07:00
26dd0af657 mockaon: Adds logic to detect external rtc toggles 2017-08-02 18:11:05 -07:00