riscv/sifive-blocks
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Adjust JTAG for rocket-chip changes

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This commit is contained in:
Megan Wachs
2017-03-14 14:52:39 -07:00
parent 25356957fe
commit 77246eaada
1 changed files with 4 additions and 3 deletions
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7
src/main/scala/devices/gpio/JTAG.scala
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@@ -19,21 +19,22 @@ class JTAGPinsIO extends Bundle {
val TMS = new GPIOPin()
val TDI = new GPIOPin()
val TDO = new GPIOPin()
val TRSTn = new GPIOPin()
val TRSTn = new GPIOPin()
}
class JTAGGPIOPort()(implicit p: Parameters) extends Module {
val io = new Bundle {
val jtag = new JTAGIO()
// TODO: make this not hard-coded true.
val jtag = new JTAGIO(hasTRSTn = true)
val pins = new JTAGPinsIO()
}
io.jtag.TCK := GPIOInputPinCtrl(io.pins.TCK, pue = Bool(true)).asClock
io.jtag.TMS := GPIOInputPinCtrl(io.pins.TMS, pue = Bool(true))
io.jtag.TDI := GPIOInputPinCtrl(io.pins.TDI, pue = Bool(true))
io.jtag.TRSTn := GPIOInputPinCtrl(io.pins.TRSTn, pue = Bool(true))
io.jtag.TRSTn.get := GPIOInputPinCtrl(io.pins.TRSTn, pue = Bool(true))
GPIOOutputPinCtrl(io.pins.TDO, io.jtag.TDO.data)
io.pins.TDO.o.oe := io.jtag.TDO.driven