riscv/sifive-blocks
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Freedom RTL blocks (https://github.com/sifive/sifive-blocks)
14 Commits 1 Branch 0 Tags 280 KiB
Scala 99.8%
Verilog 0.2%
9ca71c0cf2
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Alex Solomatnikov 9ca71c0cf2 Added note: WISHBONE interface replaced by Tilelink2
2017-02-07 16:14:28 -08:00
src/main/scala Added note: WISHBONE interface replaced by Tilelink2 2017-02-07 16:14:28 -08:00
vsrc Initial commit. 2016-11-29 04:08:44 -08:00
.gitignore Add /target to .gitignore. 2016-11-30 13:29:54 -08:00
LICENSE Initial commit. 2016-11-29 04:08:44 -08:00