riscv/sifive-blocks
1
0
Fork 0
Code Releases Activity
Freedom RTL blocks (https://github.com/sifive/sifive-blocks)
9 Commits 1 Branch 0 Tags 280 KiB
Scala 99.8%
Verilog 0.2%
2cc1012fa2
Go to file
Alex Solomatnikov 2cc1012fa2 Completed Chisel RTL (not tested yet)
2017-01-31 17:20:53 -08:00
src/main/scala Completed Chisel RTL (not tested yet) 2017-01-31 17:20:53 -08:00
vsrc Initial commit. 2016-11-29 04:08:44 -08:00
.gitignore Add /target to .gitignore. 2016-11-30 13:29:54 -08:00
LICENSE Initial commit. 2016-11-29 04:08:44 -08:00