riscv/sifive-blocks
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Freedom RTL blocks (https://github.com/sifive/sifive-blocks)
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Scala 99.8%
Verilog 0.2%
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Wesley W. Terpstra 535be3e976 spi: work around ucb-bar/chisel3#472
2017-01-31 14:03:14 -08:00
src/main/scala spi: work around ucb-bar/chisel3#472 2017-01-31 14:03:14 -08:00
vsrc Initial commit. 2016-11-29 04:08:44 -08:00
.gitignore Add /target to .gitignore. 2016-11-30 13:29:54 -08:00
LICENSE Initial commit. 2016-11-29 04:08:44 -08:00