Merge remote-tracking branch 'origin/master' into i2c
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commit
a915e84a9e
@ -30,8 +30,8 @@ class PWMGPIOPort(c: PWMBundleConfig)(implicit p: Parameters) extends Module {
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trait PeripheryPWM {
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this: TopNetwork { val pwmConfigs: Seq[PWMConfig] } =>
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val pwmDevices = (pwmConfigs.zipWithIndex) map { case (c, i) =>
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val pwm = LazyModule(new TLPWM(c) { override lazy val valName = Some(s"pwm$i") })
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val pwm = (pwmConfigs.zipWithIndex) map { case (c, i) =>
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val pwm = LazyModule(new TLPWM(c))
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pwm.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
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intBus.intnode := pwm.intnode
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pwm
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@ -52,7 +52,7 @@ trait PeripheryPWMModule {
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val outer: PeripheryPWM
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val io: PeripheryPWMBundle
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} =>
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(io.pwms.zipWithIndex zip outer.pwmDevices) foreach { case ((io, i), device) =>
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(io.pwms.zipWithIndex zip outer.pwm) foreach { case ((io, i), device) =>
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io.port := device.module.io.gpio
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}
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}
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@ -5,29 +5,29 @@ import Chisel._
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object SPIProtocol {
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val width = 2
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val Single = UInt(0, width)
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val Dual = UInt(1, width)
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val Quad = UInt(2, width)
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def Single = UInt(0, width)
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def Dual = UInt(1, width)
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def Quad = UInt(2, width)
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val cases = Seq(Single, Dual, Quad)
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def cases = Seq(Single, Dual, Quad)
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def decode(x: UInt): Seq[Bool] = cases.map(_ === x)
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}
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object SPIDirection {
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val width = 1
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val Rx = UInt(0, width)
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val Tx = UInt(1, width)
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def Rx = UInt(0, width)
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def Tx = UInt(1, width)
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}
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object SPIEndian {
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val width = 1
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val MSB = UInt(0, width)
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val LSB = UInt(1, width)
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def MSB = UInt(0, width)
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def LSB = UInt(1, width)
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}
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object SPICSMode {
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val width = 2
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val Auto = UInt(0, width)
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val Hold = UInt(2, width)
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val Off = UInt(3, width)
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def Auto = UInt(0, width)
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def Hold = UInt(2, width)
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def Off = UInt(3, width)
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}
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@ -8,8 +8,8 @@ import rocketchip.{TopNetwork,TopNetworkModule}
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trait PeripherySPI {
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this: TopNetwork { val spiConfigs: Seq[SPIConfig] } =>
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val spiDevices = (spiConfigs.zipWithIndex) map {case (c, i) =>
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val spi = LazyModule(new TLSPI(c) { override lazy val valName = Some(s"spi$i") } )
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val spi = (spiConfigs.zipWithIndex) map {case (c, i) =>
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val spi = LazyModule(new TLSPI(c))
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spi.rnode := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
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intBus.intnode := spi.intnode
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spi
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@ -28,7 +28,7 @@ trait PeripherySPIModule {
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val outer: PeripherySPI
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val io: PeripherySPIBundle
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} =>
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(io.spis zip outer.spiDevices).foreach { case (io, device) =>
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(io.spis zip outer.spi).foreach { case (io, device) =>
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io <> device.module.io.port
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}
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}
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@ -12,8 +12,8 @@ class SPIMicroOp(c: SPIConfigBase) extends SPIBundle(c) {
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}
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object SPIMicroOp {
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val Transfer = UInt(0, 1)
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val Delay = UInt(1, 1)
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def Transfer = UInt(0, 1)
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def Delay = UInt(1, 1)
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}
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class SPIPhyControl(c: SPIConfigBase) extends SPIBundle(c) {
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@ -14,8 +14,8 @@ trait PeripheryUART {
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this: TopNetwork {
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val uartConfigs: Seq[UARTConfig]
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} =>
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val uartDevices = uartConfigs.zipWithIndex.map { case (c, i) =>
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val uart = LazyModule(new UART(c) { override lazy val valName = Some(s"uart$i") } )
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val uart = uartConfigs.zipWithIndex.map { case (c, i) =>
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val uart = LazyModule(new UART(c))
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uart.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
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intBus.intnode := uart.intnode
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uart
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@ -32,7 +32,7 @@ trait PeripheryUARTModule {
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val outer: PeripheryUART
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val io: PeripheryUARTBundle
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} =>
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(io.uarts zip outer.uartDevices).foreach { case (io, device) =>
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(io.uarts zip outer.uart).foreach { case (io, device) =>
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io <> device.module.io.port
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}
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}
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@ -11,7 +11,7 @@ trait PeripheryXilinxVC707MIG extends TopNetwork {
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val xilinxvc707mig = LazyModule(new XilinxVC707MIG)
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require(p(BankedL2Config).nMemoryChannels == 1, "Coreplex must have 1 master memory port")
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val mem = Seq(xilinxvc707mig.node)
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xilinxvc707mig.node := mem(0).node
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}
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trait PeripheryXilinxVC707MIGBundle extends TopNetworkBundle {
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@ -3,10 +3,10 @@ package sifive.blocks.devices.xilinxvc707pciex1
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import Chisel._
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import diplomacy.LazyModule
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import rocketchip.{L2Crossbar,L2CrossbarModule,L2CrossbarBundle}
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import rocketchip.{TopNetwork,TopNetworkModule,TopNetworkBundle}
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import uncore.tilelink2.TLWidthWidget
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trait PeripheryXilinxVC707PCIeX1 extends L2Crossbar {
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trait PeripheryXilinxVC707PCIeX1 extends TopNetwork {
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val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
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l2.node := xilinxvc707pcie.master
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@ -15,11 +15,11 @@ trait PeripheryXilinxVC707PCIeX1 extends L2Crossbar {
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intBus.intnode := xilinxvc707pcie.intnode
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}
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trait PeripheryXilinxVC707PCIeX1Bundle extends L2CrossbarBundle {
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trait PeripheryXilinxVC707PCIeX1Bundle extends TopNetworkBundle {
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val xilinxvc707pcie = new XilinxVC707PCIeX1IO
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}
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trait PeripheryXilinxVC707PCIeX1Module extends L2CrossbarModule {
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trait PeripheryXilinxVC707PCIeX1Module extends TopNetworkModule {
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val outer: PeripheryXilinxVC707PCIeX1
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val io: PeripheryXilinxVC707PCIeX1Bundle
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@ -167,27 +167,27 @@ class vc707axi_to_pcie_x1() extends BlackBox
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class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
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{
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val slave = AXI4SlaveNode(AXI4SlavePortParameters(
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val slave = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
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slaves = Seq(AXI4SlaveParameters(
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address = List(AddressSet(0x60000000L, 0x1fffffffL)),
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executable = true,
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supportsWrite = TransferSizes(1, 256),
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supportsRead = TransferSizes(1, 256),
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interleavedId = Some(0))), // the Xilinx IP is friendly
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beatBytes = 8))
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beatBytes = 8)))
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val control = AXI4SlaveNode(AXI4SlavePortParameters(
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val control = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
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slaves = Seq(AXI4SlaveParameters(
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address = List(AddressSet(0x50000000L, 0x03ffffffL)),
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supportsWrite = TransferSizes(1, 4),
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supportsRead = TransferSizes(1, 4),
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interleavedId = Some(0))), // no read interleaving b/c AXI-lite
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beatBytes = 4))
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beatBytes = 4)))
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val master = AXI4MasterNode(AXI4MasterPortParameters(
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val master = AXI4MasterNode(Seq(AXI4MasterPortParameters(
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masters = Seq(AXI4MasterParameters(
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id = IdRange(0, 1),
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aligned = false))))
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aligned = false)))))
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lazy val module = new LazyModuleImp(this) {
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// The master on the control port must be AXI-lite
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