riscv/sifive-blocks
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jtag: The jtag interfaces have moved to a different package.

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This commit is contained in:
Megan Wachs
2017-03-02 14:46:34 -08:00
parent 072d0c1b58
commit bf9b81f2bc
1 changed files with 7 additions and 10 deletions
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17
src/main/scala/devices/gpio/JTAG.scala
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@@ -11,7 +11,7 @@ import Chisel._
// ------------------------------------------------------------
import config._
import junctions.{JTAGIO}
import jtag.{JTAGIO}
class JTAGPinsIO extends Bundle {
@@ -19,25 +19,22 @@ class JTAGPinsIO extends Bundle {
val TMS = new GPIOPin()
val TDI = new GPIOPin()
val TDO = new GPIOPin()
val TRST_n = new GPIOPin()
val TRSTn = new GPIOPin()
}
class JTAGGPIOPort(drvTdo: Boolean = false)(implicit p: Parameters) extends Module {
class JTAGGPIOPort()(implicit p: Parameters) extends Module {
val io = new Bundle {
val jtag = new JTAGIO(drvTdo)
val jtag = new JTAGIO()
val pins = new JTAGPinsIO()
}
io.jtag.TCK := GPIOInputPinCtrl(io.pins.TCK, pue = Bool(true)).asClock
io.jtag.TMS := GPIOInputPinCtrl(io.pins.TMS, pue = Bool(true))
io.jtag.TDI := GPIOInputPinCtrl(io.pins.TDI, pue = Bool(true))
io.jtag.TRST := ~GPIOInputPinCtrl(io.pins.TRST_n, pue = Bool(true))
GPIOOutputPinCtrl(io.pins.TDO, io.jtag.TDO)
if (drvTdo) {
io.pins.TDO.o.oe := io.jtag.DRV_TDO.get
}
io.jtag.TRSTn := GPIOInputPinCtrl(io.pins.TRSTn, pue = Bool(true))
GPIOOutputPinCtrl(io.pins.TDO, io.jtag.TDO.data)
io.pins.TDO.o.oe := io.jtag.TDO.driven
}