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Freedom RTL blocks (https://github.com/sifive/sifive-blocks)
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Scala 99.8%
Verilog 0.2%
6a3b5e1a31
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Jack Koenig 6a3b5e1a31 "Fix" false combinational loop through SPIArbiter 
Mux1H converts aggregates to UInt, muxes, then converts back which can
look like a cominational loop.
2017-03-30 19:12:15 -07:00
src/main/scala "Fix" false combinational loop through SPIArbiter 2017-03-30 19:12:15 -07:00
vsrc Initial commit. 2016-11-29 04:08:44 -08:00
.gitignore Add /target to .gitignore. 2016-11-30 13:29:54 -08:00
LICENSE Initial commit. 2016-11-29 04:08:44 -08:00