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riscv
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sifive-blocks
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72e4b60d81e5ae1cbc518c9a3bda486a56dfca8c
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Alex Solomatnikov
72e4b60d81
Made regs 32-bit word aligned to match the rest of the system
2017-02-09 11:36:19 -08:00
src/main
/scala
Made regs 32-bit word aligned to match the rest of the system
2017-02-09 11:36:19 -08:00
vsrc
Initial commit.
2016-11-29 04:08:44 -08:00
.gitignore
Add /target to .gitignore.
2016-11-30 13:29:54 -08:00
LICENSE
Initial commit.
2016-11-29 04:08:44 -08:00
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Description
Freedom RTL blocks (
https://github.com/sifive/sifive-blocks
)
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Scala
99.8%
Verilog
0.2%
