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Freedom RTL blocks (https://github.com/sifive/sifive-blocks)
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Scala 99.8%
Verilog 0.2%
7916ef5249
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SiFive 7916ef5249 Initial commit.
2016-11-29 04:08:44 -08:00
src/main/scala Initial commit. 2016-11-29 04:08:44 -08:00
vsrc Initial commit. 2016-11-29 04:08:44 -08:00
LICENSE Initial commit. 2016-11-29 04:08:44 -08:00