rename l2FrontendBus as fsb
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@ -13,7 +13,7 @@ import uncore.tilelink2.TLWidthWidget
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trait HasPeripheryXilinxVC707PCIeX1 extends HasTopLevelNetworks {
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val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
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l2FrontendBus.node := xilinxvc707pcie.master
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fsb.node := xilinxvc707pcie.master
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xilinxvc707pcie.slave := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
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xilinxvc707pcie.control := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
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intBus.intnode := xilinxvc707pcie.intnode
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