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riscv
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sifive-blocks
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095cb158dd0e7fe87b3cf5afa30b6db3ec4dc266
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Alex Solomatnikov
095cb158dd
Flipped polarity of output enables to match Guava pins logic
2017-02-09 11:37:40 -08:00
src/main
/scala
Flipped polarity of output enables to match Guava pins logic
2017-02-09 11:37:40 -08:00
vsrc
Initial commit.
2016-11-29 04:08:44 -08:00
.gitignore
Add /target to .gitignore.
2016-11-30 13:29:54 -08:00
LICENSE
Initial commit.
2016-11-29 04:08:44 -08:00
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Description
Freedom RTL blocks (
https://github.com/sifive/sifive-blocks
)
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Scala
99.8%
Verilog
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