riscv/sifive-blocks
1
0 Fork 0
Code Releases Activity

rename l2FrontendBus as fsb

Browse Source
This commit is contained in:
Yunsup Lee authored and Megan Wachs committed 2017-03-25 19:51:53 -07:00
1 parent faeb14dc5a
commit 3c2277447d
1 file changed
+1 -1
Download Patch File Download Diff File Expand all files Collapse all files
src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
+1 -1
View File
@@ -13,7 +13,7 @@ import uncore.tilelink2.TLWidthWidget
trait HasPeripheryXilinxVC707PCIeX1 extends HasTopLevelNetworks {
val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
l2FrontendBus.node := xilinxvc707pcie.master
fsb.node := xilinxvc707pcie.master
xilinxvc707pcie.slave := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
xilinxvc707pcie.control := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
intBus.intnode := xilinxvc707pcie.intnode