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riscv
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sifive-blocks
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c68e44ec554e47ca07e8f3e42246436779a9764f
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Wesley W. Terpstra
c68e44ec55
mig: track change to Blind port API in rocket
2017-01-19 19:53:03 -08:00
src/main
/scala
mig: track change to Blind port API in rocket
2017-01-19 19:53:03 -08:00
vsrc
Initial commit.
2016-11-29 04:08:44 -08:00
.gitignore
Add /target to .gitignore.
2016-11-30 13:29:54 -08:00
LICENSE
Initial commit.
2016-11-29 04:08:44 -08:00
Description
Freedom RTL blocks (
https://github.com/sifive/sifive-blocks
)
280
KiB
Languages
Scala
99.8%
Verilog
0.2%