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riscv/sifive-blocks
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faeb14dc5a6ade086a76a4d02806b3573a974f02
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Megan Wachs faeb14dc5a JTAG: make TRSTn optional for all helpers as well to match the IO.
2017-03-24 17:27:55 -07:00
src/main/scala
JTAG: make TRSTn optional for all helpers as well to match the IO.
2017-03-24 17:27:55 -07:00
vsrc
Initial commit.
2016-11-29 04:08:44 -08:00
.gitignore
Add /target to .gitignore.
2016-11-30 13:29:54 -08:00
LICENSE
Initial commit.
2016-11-29 04:08:44 -08:00
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Description
Freedom RTL blocks (https://github.com/sifive/sifive-blocks)
280 KiB
0 Stars 1 Watchers 0 Forks
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Scala 99.8%
Verilog 0.2%
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