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Freedom RTL blocks (https://github.com/sifive/sifive-blocks)
35 Commits 1 Branch 0 Tags 280 KiB
Scala 99.8%
Verilog 0.2%
faeb14dc5a
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Megan Wachs faeb14dc5a JTAG: make TRSTn optional for all helpers as well to match the IO.
2017-03-24 17:27:55 -07:00
src/main/scala JTAG: make TRSTn optional for all helpers as well to match the IO. 2017-03-24 17:27:55 -07:00
vsrc Initial commit. 2016-11-29 04:08:44 -08:00
.gitignore Add /target to .gitignore. 2016-11-30 13:29:54 -08:00
LICENSE Initial commit. 2016-11-29 04:08:44 -08:00