riscv/rocket-chip
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  • 7bc38383de add (non-working) blocking data cache Andrew Waterman 2016-05-20 18:59:05 -07:00
  • 3e0b5d6fd9 Ensure that a TSHR doesn't see a valid Acquire if that is blocked by a Release, but would otherwise be allocated. Colin Schmidt 2016-05-19 10:55:00 -07:00
  • fd83d20857 Use a def instead of a lazy val in ManagerCoherenceAgent. Prevents C++ emulator from randomizing inputs in unit testing. Ken McMillan 2016-05-17 17:13:48 -07:00
  • f228309bd1 add assertion to make sure SimpleHellaCacheIF doesn't get exception Howard Mao 2016-05-20 16:30:27 -07:00
  • d69446e177 Add config classes to drive unit testing of L2 TileLink agents. Ken McMillan 2016-05-17 11:00:08 -07:00
  • 87be2bcd60 make sure TraceGen addresses are correct Howard Mao 2016-05-20 16:12:11 -07:00
  • f52fc655a5 remove zscale Howard Mao 2016-05-16 13:06:45 -07:00
  • 4f84d8f757 make sure to hook up finish in ClientTileLinkEnqueuer Howard Mao 2016-05-18 13:13:34 -07:00
  • abb0e2921b return non-zero exit codes when an assertion fires Colin Schmidt 2016-05-18 11:26:50 -07:00
  • b396c68577 bump torture for priv-1.9 test-env Colin Schmidt 2016-05-17 22:02:38 -07:00
  • b0ae003981 add firrtl to regression makefile Colin Schmidt 2016-05-17 17:34:20 -07:00
  • 4aef567a80 Fix MMIO bug: replay_next wasn't set Andrew Waterman 2016-05-13 17:54:23 -07:00
  • 742c05d6a7 Pipeline D$->I$ control paths Andrew Waterman 2016-05-13 17:07:28 -07:00
  • 684d902059 Fix PLIC instantiation when S-mode is disabled Andrew Waterman 2016-05-13 11:22:46 -07:00
  • f138819992 fix order of assignments in ManagerTileLinkNetworkPort Howard Mao 2016-05-11 16:44:16 -07:00
  • 6aa708bcee Disable MMIO by default to avoid disconnected nets Andrew Waterman 2016-05-11 13:12:39 -07:00
  • 3fe00ce32a Update README.md Christopher Celio 2016-05-04 16:23:21 -07:00
  • 533b229175 Improve PLIC QoR Andrew Waterman 2016-05-10 14:15:47 -07:00
  • fbff46d27d bump rocket Andrew Waterman 2016-05-10 10:57:03 -07:00
  • aac89ca1f0 Add PLIC Andrew Waterman 2016-05-10 00:27:31 -07:00
  • e15e9c5085 First draft of interrupt controller Andrew Waterman 2016-05-10 00:25:13 -07:00
  • df479d7935 don't make MIFTagBits a computed parameter Howard Mao 2016-05-07 21:26:03 -07:00
  • 14a6e470c9 transform ids in TL -> NASTI converter if necessary Howard Mao 2016-05-07 21:19:27 -07:00
  • 3b0e9167fa add AXI to AHB converter and more conformant HASTI RAM Howard Mao 2016-04-28 18:56:27 -07:00
  • 3e759d2575 add Hasti test to unit test Howard Mao 2016-04-28 18:45:05 -07:00
  • 1ed6d6646d move NastiROM and HastiRAM into rom.scala and bram.scala Howard Mao 2016-05-02 13:58:41 -07:00
  • 77e859760c add a Hasti RAM alongside the Nasti ROM Howard Mao 2016-04-29 14:30:56 -07:00
  • 44740cb6b2 parameterize Hasti address and data bits Howard Mao 2016-04-29 17:49:26 -07:00
  • 64991d3947 add AXI to AHB converter Howard Mao 2016-04-28 18:44:35 -07:00
  • a875eb9c31 update riscv-tools for bbl fix Howard Mao 2016-05-05 19:36:34 -07:00
  • 8fa2de0816 chisel3 fix to RoCC connections honor last connect Colin Schmidt 2016-05-05 18:09:48 -07:00
  • 18ffe7b1ec don't use +verbose in vsim .run rule Howard Mao 2016-05-04 23:01:14 -07:00
  • 8b06947446 Run bmarks faster (hopefully) Andrew Waterman 2016-05-04 22:47:34 -07:00
  • f1baa4aecc update riscv-tests so that mm benchmark doesn't run forever Howard Mao 2016-05-04 12:56:27 -07:00
  • dfcb73b6c9 groundtest only needs to write to a single tohost Howard Mao 2016-05-03 20:21:13 -07:00
  • 1882e694e4 only write to a single tohost location Howard Mao 2016-05-03 20:20:52 -07:00
  • 4045a07eda Remove need for separate riscv-tests for groundtest Howard Mao 2016-05-03 17:11:25 -07:00
  • 8f891437b5 fix CacheFillTest Howard Mao 2016-05-03 13:39:04 -07:00
  • 15f4af19cf Remove HTIF CPU port Andrew Waterman 2016-05-03 13:55:59 -07:00
  • 9dd23a603a Remove HTIF port Andrew Waterman 2016-05-03 13:41:58 -07:00
  • 6cb0979ac4 fix CacheFillTest Howard Mao 2016-05-03 13:35:38 -07:00
  • 487d0b356e fixes to get groundtest working with priv-1.9 changes Howard Mao 2016-05-02 18:34:27 -07:00
  • 518d510622 only write out finish from tile 0 in groundtest Howard Mao 2016-05-03 13:09:22 -07:00
  • f26c422544 assert that TileLink router has valid route Howard Mao 2016-05-03 12:18:06 -07:00
  • b95f095aca write to multiple possible tohost locations Howard Mao 2016-05-02 20:11:20 -07:00
  • 5352497edb MPRV takes effect regardless of privilege mode Andrew Waterman 2016-05-02 19:48:39 -07:00
  • 4b4e8f7f62 fixes for priv-1.9 changes Howard Mao 2016-05-02 18:25:02 -07:00
  • 5cbcc41515 get rid of unused imports Howard Mao 2016-05-02 18:23:40 -07:00
  • be21f6962b make GlobalAddrHashMap a config variable Howard Mao 2016-05-02 18:22:43 -07:00
  • c7c8ae5468 Instantiate PRCI block Andrew Waterman 2016-05-02 18:08:33 -07:00
  • f784f4da93 Rename PRCICoreIO to PRCITileIO Andrew Waterman 2016-05-02 18:08:01 -07:00
  • cc4102f8de Add trivial version of PRCI block Andrew Waterman 2016-05-02 17:49:10 -07:00
  • 6d1e82bddf Remove mtohost/mfromhost/mipi CSRs; stub out Rocket CSR port Andrew Waterman 2016-05-02 15:21:55 -07:00
  • 72731de25a Take a stab at the PRCI-Rocket interface Andrew Waterman 2016-05-02 15:19:43 -07:00
  • 000e20f937 Remove MIPI; make mip.MSIP read-only Andrew Waterman 2016-05-02 15:18:41 -07:00
  • 83fa489cef Stop using HTIF CSR port Andrew Waterman 2016-05-02 14:40:52 -07:00
  • c4d2d29e80 Stub out debug module, rather than leaving it floating Andrew Waterman 2016-04-30 22:36:06 -07:00
  • 0ff4fd0ccd Fix IOMSHR to send finishes for stores Albert Ou 2016-04-30 22:20:29 -07:00
  • 46bbbba5e6 New address map Andrew Waterman 2016-04-30 20:59:36 -07:00
  • 695c4c5096 Support both Get and GetBlock on ROMSlave Andrew Waterman 2016-04-30 17:34:12 -07:00
  • 491184a8f8 ERET -> xRET; remove mcfgaddr Andrew Waterman 2016-04-30 17:32:51 -07:00
  • 5af98145b9 don't signal bad physical address on TLB miss Andrew Waterman 2016-04-30 17:31:46 -07:00
  • 6f052a740c Add TileLink BRAM slave Albert Ou 2016-04-29 14:10:44 -07:00
  • d0aa4c722d More WIP on new memory map Andrew Waterman 2016-04-28 16:15:31 -07:00
  • cae4265f3b Change mcfgaddr pointer Andrew Waterman 2016-04-28 16:14:05 -07:00
  • e4ace55d77 Address Map refactoring Andrew Waterman 2016-04-28 16:08:32 -07:00
  • 1df68a25fd Address Map refactoring Andrew Waterman 2016-04-28 16:08:58 -07:00
  • ed5bdf3c23 print the base address of each SCR as indicated Wei Song 2016-04-28 16:31:56 +01:00
  • 1f211b37df WIP on new memory map Andrew Waterman 2016-04-27 14:57:54 -07:00
  • 739cf07637 Remove mtime/mtimecmp Andrew Waterman 2016-04-27 14:54:51 -07:00
  • 81ff127dc3 Clean up TileLinkRecursiveInterconnect a bit Andrew Waterman 2016-04-27 14:53:11 -07:00
  • c8b1f0801b Remove start address option from AddrMapEntries Andrew Waterman 2016-04-27 14:52:05 -07:00
  • d3dee2c6c6 support countSlaves on empty address maps Andrew Waterman 2016-04-27 14:51:52 -07:00
  • 87cecc336f Add new RTC as TileLink slave, not AXI master Andrew Waterman 2016-04-27 11:55:35 -07:00
  • fb5c38c186 Handle invalidate_lr in cache arbiter, not tile Andrew Waterman 2016-04-27 11:22:04 -07:00
  • b99db83e67 Avoid needless Vec generation Andrew Waterman 2016-04-27 00:28:39 -07:00
  • 8acec8eb36 Remove dead code from BTB Andrew Waterman 2016-04-27 00:28:12 -07:00
  • eb0b5ec61e Remove stats CSR Andrew Waterman 2016-04-27 00:16:21 -07:00
  • 9044a4a4b7 Replace NastiROM with ROMSlave, which uses TileLink Andrew Waterman 2016-04-27 00:15:00 -07:00
  • 356efe2fd5 Simplify TileLink Narrower Andrew Waterman 2016-04-26 16:44:54 -07:00
  • fe8c91f620 Fix IOMSHR state machine bug Andrew Waterman 2016-04-26 15:30:24 -07:00
  • 5fd5b58743 Remove stats CSR Andrew Waterman 2016-04-25 17:57:48 -07:00
  • d93677a343 Support larger cache sets when not using VM Andrew Waterman 2016-04-25 17:55:22 -07:00
  • 5dbf9640e2 Use TLB flush signal to I$ explicitly Yunsup Lee 2016-04-22 15:41:31 -07:00
  • 84fd45fd77 Pass TLB flush signal to I$ explicitly Andrew Waterman 2016-04-22 15:20:17 -07:00
  • 48170fd9aa add default cases to configs that use CDEMatchError Colin Schmidt 2016-04-21 19:37:08 -07:00
  • f6e44b1348 avoid logical to physical header conversion overflow Wei Song 2016-04-22 17:47:34 +01:00
  • f7af908969 put memory into the address map and no longer use MMIOBase Howard Mao 2016-04-21 15:47:46 -07:00
  • b7527268bb use address map instead of MMIOBase to find size of memory Howard Mao 2016-04-21 15:34:28 -07:00
  • 5e793427eb use address map instead of MMIOBase Howard Mao 2016-04-21 15:38:43 -07:00
  • f9de99ed40 changes to match junctions no-mmio-base Howard Mao 2016-04-21 15:35:37 -07:00
  • 6260ad56e8 stop using MMIOBase and encode cacheability in address map Howard Mao 2016-04-21 15:33:53 -07:00
  • 325d3671c4 add write data id field for AXI3 compat Howard Mao 2016-04-19 10:03:10 -07:00
  • 0cf6b1f118 merge ATOS changes from hurricane Howard Mao 2016-04-19 09:48:27 -07:00
  • c19931ba03 add technical report to readme Scott Beamer 2016-04-19 15:24:13 -07:00
  • 4afc9c69a0 streamline sbt Yunsup Lee 2016-04-19 14:22:22 -07:00
  • 9b3faff5a5 add id field to write data channel in TL -> AXI converter Howard Mao 2016-04-19 09:46:31 -07:00
  • 1967186a96 add id field to NastiWriteDataChannel Howard Mao 2016-04-19 09:38:04 -07:00
  • 42c4d1e51f add NastiMemoryDemux Howard Mao 2016-02-24 23:10:22 -08:00
  • 0bf8d07aba make AtosSerializedIO clock divisible Howard Mao 2016-02-24 23:10:06 -08:00