Address Map refactoring
This commit is contained in:
Andrew Waterman
parent
c8b1f0801b
commit
e4ace55d77
@ -32,25 +32,30 @@ trait HasAddrMapParameters {
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val addrMap = new AddrHashMap(p(GlobalAddrMap))
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}
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case class MemAttr(prot: Int, cacheable: Boolean = false)
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abstract class MemRegion {
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def align: BigInt
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def size: BigInt
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def numSlaves: Int
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}
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case class MemSize(size: BigInt, prot: Int, cacheable: Boolean = false) extends MemRegion {
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case class MemSize(size: BigInt, align: BigInt, attr: MemAttr) extends MemRegion {
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def numSlaves = 1
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}
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case class MemSubmap(size: BigInt, entries: AddrMap) extends MemRegion {
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val numSlaves = entries.countSlaves
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val align = entries.computeAlign
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}
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object AddrMapConsts {
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object AddrMapProt {
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val R = 0x1
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val W = 0x2
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val X = 0x4
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val RW = R | W
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val RX = R | X
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val RWX = R | W | X
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val SZ = 3
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}
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class AddrMapProt extends Bundle {
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@ -61,15 +66,21 @@ class AddrMapProt extends Bundle {
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case class AddrMapEntry(name: String, region: MemRegion)
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case class AddrHashMapEntry(port: Int, start: BigInt, size: BigInt, prot: Int, cacheable: Boolean)
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case class AddrHashMapEntry(port: Int, start: BigInt, region: MemRegion)
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class AddrMap(entries: Seq[AddrMapEntry]) extends scala.collection.IndexedSeq[AddrMapEntry] {
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private val hash = HashMap(entries.map(e => (e.name, e.region)):_*)
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def apply(index: Int): AddrMapEntry = entries(index)
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def length: Int = entries.size
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def countSlaves: Int = entries.map(_.region.numSlaves).foldLeft(0)(_ + _)
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def computeSize: BigInt = new AddrHashMap(this).size
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def computeAlign: BigInt = entries.map(_.region.align).foldLeft(BigInt(1))(_ max _)
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override def tail: AddrMap = new AddrMap(entries.tail)
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}
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@ -78,68 +89,68 @@ object AddrMap {
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}
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class AddrHashMap(addrmap: AddrMap, start: BigInt = BigInt(0)) {
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val mapping = new HashMap[String, AddrHashMapEntry]
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private val mapping = HashMap[String, AddrHashMapEntry]()
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private val subMaps = HashMap[String, AddrHashMapEntry]()
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private def genPairs(am: AddrMap, start: BigInt): Seq[(String, AddrHashMapEntry)] = {
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var ind = 0
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private def genPairs(am: AddrMap, start: BigInt, startIdx: Int, prefix: String): (BigInt, Int) = {
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var ind = startIdx
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var base = start
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var pairs = Seq[(String, AddrHashMapEntry)]()
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am.foreach {
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case AddrMapEntry(name, MemSize(size, prot, cacheable)) =>
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pairs = (name, AddrHashMapEntry(ind, base, size, prot, cacheable)) +: pairs
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base += size
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am.foreach { ame =>
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val name = prefix + ame.name
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base = (base + ame.region.align - 1) / ame.region.align * ame.region.align
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ame.region match {
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case r: MemSize =>
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mapping += name -> AddrHashMapEntry(ind, base, r)
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base += r.size
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ind += 1
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case AddrMapEntry(name, MemSubmap(size, submap)) =>
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val subpairs = genPairs(submap, base).map {
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case (subname, AddrHashMapEntry(subind, subbase, subsize, prot, cacheable)) =>
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(name + ":" + subname,
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AddrHashMapEntry(ind + subind, subbase, subsize, prot, cacheable))
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}
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pairs = subpairs ++ pairs
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ind += subpairs.size
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base += size
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}
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pairs
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case r: MemSubmap =>
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subMaps += name -> AddrHashMapEntry(-1, base, r)
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ind = genPairs(r.entries, base, ind, name + ":")._2
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base += r.size
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}}
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(base, ind)
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}
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for ((name, ind) <- genPairs(addrmap, start)) { mapping(name) = ind }
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val size = genPairs(addrmap, start, 0, "")._1
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def nEntries: Int = mapping.size
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def apply(name: String): AddrHashMapEntry = mapping(name)
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def get(name: String): Option[AddrHashMapEntry] = mapping.get(name)
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def sortedEntries(): Seq[(String, BigInt, BigInt, Int, Boolean)] = {
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val arr = new Array[(String, BigInt, BigInt, Int, Boolean)](mapping.size)
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mapping.foreach { case (name, AddrHashMapEntry(port, base, size, prot, cacheable)) =>
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arr(port) = (name, base, size, prot, cacheable)
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val sortedEntries: Seq[(String, BigInt, MemSize)] = {
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val arr = new Array[(String, BigInt, MemSize)](mapping.size)
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mapping.foreach { case (name, AddrHashMapEntry(port, base, region)) =>
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arr(port) = (name, base, region.asInstanceOf[MemSize])
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}
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arr.toSeq
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}
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def nEntries: Int = mapping.size
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def apply(name: String): AddrHashMapEntry = mapping.getOrElse(name, subMaps(name))
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def subMap(name: String): (BigInt, AddrMap) = {
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val m = subMaps(name)
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(m.start, m.region.asInstanceOf[MemSubmap].entries)
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}
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def isInRegion(name: String, addr: UInt): Bool = {
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val start = mapping(name).start
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val size = mapping(name).size
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val size = mapping(name).region.size
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UInt(start) <= addr && addr < UInt(start + size)
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}
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def isCacheable(addr: UInt): Bool = {
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sortedEntries().map { case (_, base, size, _, cacheable) =>
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UInt(base) <= addr && addr < UInt(base + size) && Bool(cacheable)
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}.reduce(_ || _)
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sortedEntries.filter(_._3.attr.cacheable).map { case (_, base, region) =>
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UInt(base) <= addr && addr < UInt(base + region.size)
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}.foldLeft(Bool(false))(_ || _)
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}
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def isValid(addr: UInt): Bool = {
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addr < UInt(start) || sortedEntries().map {
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case (_, base, size, _, _) =>
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addr >= UInt(base) && addr < UInt(base + size)
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}.reduceLeft(_ || _)
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sortedEntries.map { case (_, base, region) =>
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addr >= UInt(base) && addr < UInt(base + region.size)
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}.foldLeft(Bool(false))(_ || _)
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}
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def getProt(addr: UInt): AddrMapProt = {
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val protBits = Mux(addr < UInt(start),
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Bits(AddrMapConsts.RWX, 3),
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Mux1H(sortedEntries().map { case (_, base, size, prot, _) =>
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(addr >= UInt(base) && addr < UInt(base + size), Bits(prot, 3))
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}))
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new AddrMapProt().fromBits(protBits)
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val protForRegion = sortedEntries.map { case (_, base, region) =>
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val inRegion = addr >= UInt(base) && addr < UInt(base + region.size)
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Mux(inRegion, UInt(region.attr.prot, AddrMapProt.SZ), UInt(0))
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}
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new AddrMapProt().fromBits(protForRegion.reduce(_|_))
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}
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}
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@ -502,53 +502,33 @@ class NastiRecursiveInterconnect(
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val nMasters: Int, val nSlaves: Int,
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addrmap: AddrMap, base: BigInt)
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(implicit p: Parameters) extends NastiInterconnect()(p) {
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var lastEnd = base
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var slaveInd = 0
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val levelSize = addrmap.size
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val realAddrMap = addrmap map { case AddrMapEntry(name, region) =>
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val start = lastEnd
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val size = region.size
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require(isPow2(size),
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s"Region $name size $size is not a power of 2")
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require(start % size == 0,
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f"Region $name start address 0x$start%x not divisible by 0x$size%x" )
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require(start >= lastEnd,
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f"Region $name start address 0x$start%x before previous region end")
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lastEnd = start + size
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(start, size)
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}
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val addrHashMap = new AddrHashMap(addrmap, base)
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val routeSel = (addr: UInt) => {
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Vec(realAddrMap.map { case (start, size) =>
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addr >= UInt(start) && addr < UInt(start + size)
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}).toBits
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Cat(addrmap.map { case entry =>
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val hashEntry = addrHashMap(entry.name)
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addr >= UInt(hashEntry.start) && addr < UInt(hashEntry.start + hashEntry.region.size)
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}.reverse)
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}
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val xbar = Module(new NastiCrossbar(nMasters, levelSize, routeSel))
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xbar.io.masters <> io.masters
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addrmap.zip(realAddrMap).zip(xbar.io.slaves).zipWithIndex.foreach {
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case (((entry, (start, size)), xbarSlave), i) => {
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io.slaves <> addrmap.zip(xbar.io.slaves).flatMap {
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case (entry, xbarSlave) => {
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entry.region match {
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case MemSize(_, _, _) =>
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io.slaves(slaveInd) <> xbarSlave
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slaveInd += 1
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case _: MemSize =>
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Some(xbarSlave)
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case MemSubmap(_, submap) if submap.isEmpty =>
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val err_slave = Module(new NastiErrorSlave)
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err_slave.io <> xbarSlave
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None
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case MemSubmap(_, submap) =>
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if (submap.isEmpty) {
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val err_slave = Module(new NastiErrorSlave)
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err_slave.io <> xbarSlave
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} else {
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val subSlaves = submap.countSlaves
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val outputs = io.slaves.drop(slaveInd).take(subSlaves)
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val ic = Module(new NastiRecursiveInterconnect(1, subSlaves, submap, start))
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ic.io.masters.head <> xbarSlave
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for ((o, s) <- outputs zip ic.io.slaves)
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o <> s
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slaveInd += subSlaves
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}
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val subSlaves = submap.countSlaves
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val ic = Module(new NastiRecursiveInterconnect(1, subSlaves, submap, addrHashMap(entry.name).start))
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ic.io.masters.head <> xbarSlave
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ic.io.slaves
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}
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}
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}
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