add Hasti test to unit test
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1882e694e4
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@ -13,6 +13,80 @@ abstract class UnitTest extends Module {
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}
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}
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class HastiTestDriver(implicit p: Parameters) extends NastiModule {
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val io = new Bundle {
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val nasti = new NastiIO
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val finished = Bool(OUTPUT)
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val start = Bool(INPUT)
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}
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val (write_cnt, write_done) = Counter(io.nasti.w.fire(), 8)
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val (read_cnt, read_done) = Counter(io.nasti.r.fire(), 8)
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val write_data = UInt(0x1000, 32) | write_cnt
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val expected_data = UInt(0x1000, 32) | read_cnt
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val (s_idle :: s_write_addr :: s_write_data :: s_write_stall :: s_write_resp ::
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s_read_addr :: s_read_data :: s_read_stall :: s_done :: Nil) = Enum(Bits(), 9)
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val state = Reg(init = s_idle)
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io.nasti.aw.valid := (state === s_write_addr)
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io.nasti.aw.bits := NastiWriteAddressChannel(
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id = UInt(0),
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addr = UInt(0),
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size = UInt("b010"),
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len = UInt(7))
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io.nasti.w.valid := (state === s_write_data)
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io.nasti.w.bits := NastiWriteDataChannel(
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data = Cat(write_data, write_data),
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last = (write_cnt === UInt(7)))
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io.nasti.b.ready := (state === s_write_resp)
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io.nasti.ar.valid := (state === s_read_addr)
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io.nasti.ar.bits := NastiReadAddressChannel(
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id = UInt(0),
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addr = UInt(0),
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size = UInt("b010"),
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len = UInt(7))
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io.nasti.r.ready := (state === s_read_data)
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io.finished := (state === s_done)
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when (state === s_idle && io.start) { state := s_write_addr }
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when (io.nasti.aw.fire()) { state := s_write_data }
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when (io.nasti.w.fire()) { state := s_write_stall }
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when (state === s_write_stall) { state := s_write_data }
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when (write_done) { state := s_write_resp }
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when (io.nasti.b.fire()) { state := s_read_addr }
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when (io.nasti.ar.fire()) { state := s_read_data }
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when (io.nasti.r.fire()) { state := s_read_stall }
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when (state === s_read_stall) { state := s_read_data }
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when (read_done) { state := s_done }
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val read_data = Mux(read_cnt(0),
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io.nasti.r.bits.data(63, 32),
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io.nasti.r.bits.data(31, 0))
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assert(!io.nasti.r.valid || read_data === expected_data,
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"HastiTest got wrong data")
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}
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class HastiTest(implicit p: Parameters) extends UnitTest {
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val sram = Module(new HastiRAM(8))
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val bus = Module(new HastiBus(Seq(a => Bool(true))))
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val conv = Module(new HastiMasterIONastiIOConverter)
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val driver = Module(new HastiTestDriver)
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bus.io.slaves(0) <> sram.io
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bus.io.master <> conv.io.hasti
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conv.io.nasti <> driver.io.nasti
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io.finished := driver.io.finished
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driver.io.start := io.start
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}
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class NastiDemuxDriver(n: Int)(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val start = Bool(INPUT)
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@ -519,7 +593,8 @@ class UnitTestSuite(implicit p: Parameters) extends GroundTest()(p) {
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Module(new NastiIOHostIOConverterTest),
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Module(new TileLinkToSmiConverterTest),
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Module(new AtosConverterTest),
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Module(new NastiMemoryDemuxTest))
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Module(new NastiMemoryDemuxTest),
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Module(new HastiTest))
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val s_idle :: s_start :: s_wait :: Nil = Enum(Bits(), 3)
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val state = Reg(init = s_idle)
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