riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

add NastiMemoryDemux

Browse Source
This commit is contained in:
Howard Mao 2016-02-24 23:10:22 -08:00
parent 0bf8d07aba
commit 42c4d1e51f
1 changed files with 36 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
junctions/src/main/scala/nasti.scala
View File

@ -681,3 +681,39 @@ class NastiMemorySelector(nBanks: Int, maxMemChannels: Int, configs: Seq[Int])
muxOnSelect(ic.io.slaves, io.slaves, io.select === UInt(select))
}
}
class NastiMemoryDemux(nRoutes: Int)(implicit p: Parameters) extends NastiModule()(p) {
val io = new Bundle {
val master = (new NastiIO).flip
val slaves = Vec(nRoutes, new NastiIO)
val select = UInt(INPUT, log2Up(nRoutes))
}
def connectReqChannel[T <: Data](idx: Int, out: DecoupledIO[T], in: DecoupledIO[T]) {
out.valid := in.valid && io.select === UInt(idx)
out.bits := in.bits
when (io.select === UInt(idx)) { in.ready := out.ready }
}
def connectRespChannel[T <: Data](idx: Int, out: DecoupledIO[T], in: DecoupledIO[T]) {
when (io.select === UInt(idx)) { out.valid := in.valid }
when (io.select === UInt(idx)) { out.bits := in.bits }
in.ready := out.ready && io.select === UInt(idx)
}
io.master.ar.ready := Bool(false)
io.master.aw.ready := Bool(false)
io.master.w.ready := Bool(false)
io.master.r.valid := Bool(false)
io.master.r.bits := NastiReadDataChannel(id = UInt(0), data = UInt(0))
io.master.b.valid := Bool(false)
io.master.b.bits := NastiWriteResponseChannel(id = UInt(0))
io.slaves.zipWithIndex.foreach { case (slave, i) =>
connectReqChannel(i, slave.ar, io.master.ar)
connectReqChannel(i, slave.aw, io.master.aw)
connectReqChannel(i, slave.w, io.master.w)
connectRespChannel(i, io.master.r, slave.r)
connectRespChannel(i, io.master.b, slave.b)
}
}