remove zscale
This commit is contained in:
Howard Mao
parent
abb0e2921b
commit
f52fc655a5
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@ -19,9 +19,6 @@
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[submodule "fpga-zynq"]
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path = fpga-zynq
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url = https://github.com/ucb-bar/fpga-zynq.git
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[submodule "zscale"]
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path = zscale
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url = https://github.com/ucb-bar/zscale
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[submodule "junctions"]
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path = junctions
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url = https://github.com/ucb-bar/junctions
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@ -16,7 +16,6 @@ cache:
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rocket/target
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target
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uncore/target
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zscale/target
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# packages needed to build riscv-tools
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addons:
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2
Makefrag
2
Makefrag
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@ -22,7 +22,7 @@ CHISEL_ARGS := --W0W --minimumCompatibility 3.0.0 --backend $(BACKEND) --configN
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endif
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src_path = src/main/scala
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default_submodules = . junctions uncore hardfloat rocket zscale groundtest context-dependent-environments
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default_submodules = . junctions uncore hardfloat rocket groundtest context-dependent-environments
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chisel_srcs = $(addprefix $(base_dir)/,$(addsuffix /$(src_path)/*.scala,$(default_submodules) $(ROCKETCHIP_ADDONS)))
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disasm := 2>
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@ -7,7 +7,6 @@ sim_dir = .
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output_dir = $(sim_dir)/output
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BACKEND = c
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#CONFIG ?= ZscaleConfig
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CONFIG ?= DefaultCPPConfig
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include $(base_dir)/Makefrag
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@ -21,9 +21,8 @@ object BuildSettings extends Build {
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lazy val junctions = project.dependsOn(chisel, cde)
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lazy val uncore = project.dependsOn(junctions)
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lazy val rocket = project.dependsOn(hardfloat, uncore)
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lazy val zscale = project.dependsOn(rocket)
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lazy val groundtest = project.dependsOn(rocket)
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lazy val rocketchip = (project in file(".")).settings(chipSettings).dependsOn(zscale, groundtest)
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lazy val rocketchip = (project in file(".")).settings(chipSettings).dependsOn(groundtest)
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lazy val addons = settingKey[Seq[String]]("list of addons used for this build")
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lazy val make = inputKey[Unit]("trigger backend-specific makefile command")
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@ -70,7 +70,7 @@ fsim-asm-tests: stamps/$(CONFIG)/fsim-asm-tests.stamp
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fsim-bmark-tests: stamps/$(CONFIG)/fsim-bmark-tests.stamp
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fsim-torture: stamps/$(CONFIG)/fsim-torture-$(TORTURE_CONFIG).stamp
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submodule_names = chisel2 chisel3 context-dependent-environments dramsim2 firrtl groundtest hardfloat junctions rocket torture uncore zscale $(ROCKETCHIP_ADDONS)
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submodule_names = chisel2 chisel3 context-dependent-environments dramsim2 firrtl groundtest hardfloat junctions rocket torture uncore $(ROCKETCHIP_ADDONS)
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# Checks out all the rocket-chip submodules
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stamps/other-submodules.stamp:
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@ -7,7 +7,6 @@ import junctions._
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import uncore._
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import rocket._
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import rocket.Util._
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import zscale._
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import groundtest._
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import scala.math.max
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import DefaultTestSuites._
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@ -387,21 +386,6 @@ class DefaultL2FPGAConfig extends Config(new WithL2Capacity64 ++ new WithL2Cache
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class PLRUL2Config extends Config(new WithPLRU ++ new DefaultL2Config)
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class WithZscale extends Config(
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(pname,site,here) => pname match {
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case XLen => 32
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case UseFPU => false
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case BuildZscale => {
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TestGeneration.addSuites(List(rv32ui("p"), rv32um("p")))
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TestGeneration.addSuites(List(zscaleBmarks))
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(r: Bool, p: Parameters) => Module(new Zscale(r)(p))
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}
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case BootROMCapacity => Dump("BOOT_CAPACITY", 16*1024)
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case DRAMCapacity => Dump("DRAM_CAPACITY", 64*1024*1024)
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case _ => throw new CDEMatchError
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}
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)
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class WithRV32 extends Config(
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(pname,site,here) => pname match {
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case XLen => 32
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@ -411,8 +395,6 @@ class WithRV32 extends Config(
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}
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)
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class ZscaleConfig extends Config(new WithZscale ++ new DefaultConfig)
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class FPGAConfig extends Config (
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(pname,site,here) => pname match {
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case NAcquireTransactors => 4
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@ -154,9 +154,6 @@ object DefaultTestSuites {
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List("ad","ae","af","ag","ai","ak","al","am","an","ap","aq","ar","at","av","ay","az",
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"bb","bc","bf","bh","bj","bk","bm","bo","br","bs","ce","cf","cg","ci","ck","cl",
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"cm","cs","cv","cy","dc","df","dm","do","dr","ds","du","dv").map(_+"_matmul")): _*))
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val zscaleBmarks = new BenchmarkTestSuite("zscale", "$(base_dir)/zscale/sw", LinkedHashSet(
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"led", "mbist"))
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}
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object TestGenerator extends App with FileSystemUtilities {
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@ -1,77 +0,0 @@
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// See LICENSE for license details.
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package rocketchip
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import Chisel._
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import cde.{Parameters, Field}
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import junctions._
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import uncore._
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import rocket._
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import zscale._
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case object UseZscale extends Field[Boolean]
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case object BuildZscale extends Field[(Bool, Parameters) => Zscale]
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case object BootROMCapacity extends Field[Int]
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case object DRAMCapacity extends Field[Int]
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class ZscaleSystem(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val host = new HtifIO
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val jtag = new HastiMasterIO().flip
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val bootmem = new HastiSlaveIO().flip
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val dram = new HastiSlaveIO().flip
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val spi = new HastiSlaveIO().flip
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val led = new PociIO
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val corereset = new PociIO
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}
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val core = p(BuildZscale)(io.host.reset, p)
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val bootmem_afn = (addr: UInt) => addr(31, 14) === UInt(0)
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val sbus_afn = (addr: UInt) => addr(31, 29).orR
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val dram_afn = (addr: UInt) => addr(31, 26) === UInt(8)
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val spi_afn = (addr: UInt) => addr(31, 26) === UInt(9) && addr(25, 14) === UInt(0)
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val pbus_afn = (addr: UInt) => addr(31) === UInt(1)
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val led_afn = (addr: UInt) => addr(31) === UInt(1) && addr(30, 10) === UInt(0)
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val corereset_afn = (addr: UInt) => addr(31) === UInt(1) && addr(30, 10) === UInt(1)
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val xbar = Module(new HastiXbar(3, Seq(bootmem_afn, sbus_afn)))
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val sadapter = Module(new HastiSlaveToMaster)
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val sbus = Module(new HastiBus(Seq(dram_afn, spi_afn, pbus_afn)))
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val padapter = Module(new HastiToPociBridge)
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val pbus = Module(new PociBus(Seq(led_afn, corereset_afn)))
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core.io.host <> io.host
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xbar.io.masters(0) <> io.jtag
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xbar.io.masters(1) <> core.io.dmem
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xbar.io.masters(2) <> core.io.imem
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io.bootmem <> xbar.io.slaves(0)
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sadapter.io.in <> xbar.io.slaves(1)
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sbus.io.master <> sadapter.io.out
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io.dram <> sbus.io.slaves(0)
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io.spi <> sbus.io.slaves(1)
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padapter.io.in <> sbus.io.slaves(2)
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pbus.io.master <> padapter.io.out
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io.led <> pbus.io.slaves(0)
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io.corereset <> pbus.io.slaves(1)
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}
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class ZscaleTop(topParams: Parameters) extends Module {
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implicit val p = topParams.alterPartial({case TLId => "L1toL2" })
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val io = new Bundle {
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val host = new HtifIO
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}
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val sys = Module(new ZscaleSystem)
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val bootmem = Module(new HastiSRAM(p(BootROMCapacity)/4))
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val dram = Module(new HastiSRAM(p(DRAMCapacity)/4))
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sys.io.host <> io.host
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bootmem.io <> sys.io.bootmem
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dram.io <> sys.io.dram
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}
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@ -1,95 +0,0 @@
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// See LICENSE for license details.
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//
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module ZscaleTestHarness;
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reg clk = 0;
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reg reset = 1;
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always #`CLOCK_PERIOD clk = ~clk;
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wire csr_resp_valid;
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wire [31:0] dummy;
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wire [31:0] csr_resp_bits;
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ZscaleTop dut
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(
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.clk(clk),
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.reset(reset),
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.io_host_reset(reset),
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.io_host_id(1'd0),
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.io_host_csr_req_ready(),
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.io_host_csr_req_valid(1'b1),
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.io_host_csr_req_bits_rw(1'b0),
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.io_host_csr_req_bits_addr(12'h780), // tohost register
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.io_host_csr_req_bits_data({dummy, 32'd0}),
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.io_host_csr_resp_ready(1'b1),
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.io_host_csr_resp_valid(csr_resp_valid),
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.io_host_csr_resp_bits({dummy, csr_resp_bits})
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);
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reg [1023:0] loadmem = 0;
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reg [1023:0] vcdplusfile = 0;
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reg [ 63:0] max_cycles = 0;
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reg [ 63:0] trace_count = 0;
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reg verbose = 0;
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wire printf_cond = verbose && !reset;
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integer stderr = 32'h80000002;
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integer i;
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reg [127:0] image [8191:0];
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initial
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begin
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$value$plusargs("max-cycles=%d", max_cycles);
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verbose = $test$plusargs("verbose");
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if ($value$plusargs("loadmem=%s", loadmem))
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begin
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$readmemh(loadmem, image);
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end
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if ($value$plusargs("vcdplusfile=%s", vcdplusfile))
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begin
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$vcdplusfile(vcdplusfile);
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$vcdpluson(0);
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$vcdplusmemon(0);
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end
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#0.5;
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for (i=0; i<`BOOT_CAPACITY/16; i=i+1) begin
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dut.bootmem.ram.ram[4*i+0] = image[i][31:0];
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dut.bootmem.ram.ram[4*i+1] = image[i][63:32];
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dut.bootmem.ram.ram[4*i+2] = image[i][95:64];
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dut.bootmem.ram.ram[4*i+3] = image[i][127:96];
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end
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#777.7 reset = 0;
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end
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reg [255:0] reason = 0;
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always @(posedge clk)
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begin
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trace_count = trace_count + 1;
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if (max_cycles > 0 && trace_count > max_cycles)
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reason = "timeout";
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if (!reset)
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begin
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if (csr_resp_valid && csr_resp_bits > 1)
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$sformat(reason, "tohost = %d", csr_resp_bits >> 1);
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if (csr_resp_valid && csr_resp_bits == 1)
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begin
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$vcdplusclose;
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$finish;
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end
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end
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if (reason)
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begin
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$fdisplay(stderr, "*** FAILED *** (%s) after %d simulation cycles", reason, trace_count);
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$vcdplusclose;
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$finish;
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end
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end
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endmodule
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1
zscale
1
zscale
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@ -1 +0,0 @@
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Subproject commit d430f0ae5bb5c32cc9d7f8c1743948667ac47246
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