riscv/rocket-chip
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Use TLB flush signal to I$ explicitly

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This commit is contained in:
Yunsup Lee 2016-04-22 15:41:31 -07:00
parent 84fd45fd77
commit 5dbf9640e2
1 changed files with 1 additions and 1 deletions
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2
rocket/src/main/scala/frontend.scala
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@ -106,7 +106,7 @@ class Frontend(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePa
icache.io.req.bits.idx := io.cpu.npc
icache.io.invalidate := io.cpu.flush_icache
icache.io.s1_ppn := tlb.io.resp.ppn
icache.io.s1_kill := io.cpu.req.valid || tlb.io.resp.miss || tlb.io.resp.xcpt_if || icmiss || io.ptw.invalidate
icache.io.s1_kill := io.cpu.req.valid || tlb.io.resp.miss || tlb.io.resp.xcpt_if || icmiss || io.cpu.flush_tlb
io.cpu.resp.valid := s2_valid && (s2_xcpt_if || s2_resp_valid)
io.cpu.resp.bits.pc := s2_pc