riscv/rocket-chip
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chisel3 fix to RoCC connections honor last connect

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This commit is contained in:
Colin Schmidt 2016-05-05 18:09:48 -07:00
parent 9dd23a603a
commit 8fa2de0816
1 changed files with 2 additions and 1 deletions
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rocket/src/main/scala/rocket.scala
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@ -429,7 +429,8 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
csr.io.prci <> io.prci
io.fpu.fcsr_rm := csr.io.fcsr_rm
csr.io.fcsr_flags := io.fpu.fcsr_flags
csr.io.rocc <> io.rocc
io.rocc.csr <> csr.io.rocc.csr
csr.io.rocc.interrupt <> io.rocc.interrupt
csr.io.pc := wb_reg_pc
csr.io.uarch_counters.foreach(_ := Bool(false))
io.ptw.ptbr := csr.io.ptbr