riscv/rocket-chip
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use address map instead of MMIOBase to find size of memory

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Howard Mao 2016-04-21 15:34:28 -07:00 committed by Andrew Waterman
parent 2d6f35525e
commit b7527268bb
4 changed files with 9 additions and 7 deletions
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3
rocket/src/main/scala/csr.scala
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@ -8,6 +8,7 @@ import Instructions._
import cde.{Parameters, Field}
import uncore._
import scala.math._
import junctions.{AddrHashMap, GlobalAddrMap}
class MStatus extends Bundle {
val prv = UInt(width = PRV.SZ) // not truly part of mstatus, but convenient
@ -227,7 +228,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
CSRs.misa -> UInt(isa),
CSRs.mstatus -> read_mstatus,
CSRs.mtvec -> reg_mtvec,
CSRs.mcfgaddr -> UInt(p(junctions.MMIOBase)),
CSRs.mcfgaddr -> UInt(addrMap("mem").size),
CSRs.mipi -> reg_mip.msip,
CSRs.mip -> read_mip,
CSRs.mie -> reg_mie,

8
rocket/src/main/scala/dma.scala
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@ -3,7 +3,7 @@ package rocket
import Chisel._
import uncore._
import uncore.DmaRequest._
import junctions.ParameterizedBundle
import junctions.{ParameterizedBundle, AddrHashMap, GlobalAddrMap}
import cde.Parameters
trait HasClientDmaParameters extends HasCoreParameters with HasDmaParameters {
@ -165,8 +165,10 @@ class DmaFrontend(implicit p: Parameters) extends CoreModule()(p)
}
def check_region(cmd: UInt, src: UInt, dst: UInt): Bool = {
val dst_ok = Mux(cmd === DMA_CMD_SOUT, dst >= UInt(mmioBase), dst < UInt(mmioBase))
val src_ok = Mux(cmd === DMA_CMD_SIN, src >= UInt(mmioBase), Bool(true))
val src_cacheable = addrMap.isCacheable(src)
val dst_cacheable = addrMap.isCacheable(dst)
val dst_ok = Mux(cmd === DMA_CMD_SOUT, !dst_cacheable, dst_cacheable)
val src_ok = Mux(cmd === DMA_CMD_SIN, !src_cacheable, Bool(true))
dst_ok && src_ok
}

4
rocket/src/main/scala/nbdcache.scala
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@ -421,8 +421,8 @@ class MSHRFile(implicit p: Parameters) extends L1HellaCacheModule()(p) {
val fence_rdy = Bool(OUTPUT)
}
// determine if the request is in the memory region or mmio region
val cacheable = io.req.bits.addr < UInt(mmioBase)
// determine if the request is cacheable or not
val cacheable = addrMap.isCacheable(io.req.bits.addr)
val sdq_val = Reg(init=Bits(0, sdqDepth))
val sdq_alloc_id = PriorityEncoder(~sdq_val(sdqDepth-1,0))

1
rocket/src/main/scala/rocket.scala
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@ -48,7 +48,6 @@ trait HasCoreParameters extends HasAddrMapParameters {
val vpnBitsExtended = vpnBits + (vaddrBits < xLen).toInt
val vaddrBitsExtended = vpnBitsExtended + pgIdxBits
val coreMaxAddrBits = paddrBits max vaddrBitsExtended
val mmioBase = p(MMIOBase)
val nCustomMrwCsrs = p(NCustomMRWCSRs)
val roccCsrs = if (p(BuildRoCC).isEmpty) Nil
else p(BuildRoCC).flatMap(_.csrs)