riscv/rocket-chip
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add AXI to AHB converter and more conformant HASTI RAM

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This commit is contained in:
Howard Mao 2016-04-28 18:56:27 -07:00
parent a875eb9c31
commit 3b0e9167fa
4 changed files with 6 additions and 3 deletions
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2
groundtest

@ -1 +1 @@
Subproject commit 11b046a0bc0c23fa23ced1fa890af183922d2ec4
Subproject commit 49b713c4fbb6660b6d86a7e19ea048d6d7aeb17a

2
junctions

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Subproject commit 7448c2726721b0260ce56e1dfc03d6f7786a2f9b
Subproject commit 7aaaa59d96f998d38d0969894cf9ec0e1fcfed22

3
src/main/scala/Configs.scala
View File

@ -118,6 +118,9 @@ class DefaultConfig extends Config (
addrBits = Dump("MEM_ADDR_BITS", site(PAddrBits)),
idBits = Dump("MEM_ID_BITS", site(MIFTagBits)))
}
case HastiKey => HastiParameters(
dataBits = site(XLen),
addrBits = site(PAddrBits))
//Params used by all caches
case NSets => findBy(CacheName)
case NWays => findBy(CacheName)

2
uncore

@ -1 +1 @@
Subproject commit 8e21cc781f5fd1fdfd94a579fb5a1392ed664e99
Subproject commit f236b5fa0dbc3ab488b5ac021862808f11361524