add AXI to AHB converter and more conformant HASTI RAM

2016-04-28 18:56:27 -07:00
parent a875eb9c31
commit 3b0e9167fa
4 changed files with 6 additions and 3 deletions
--- a/2
+++ b/2
--- a/2
+++ b/2
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@ -118,6 +118,9 @@ class DefaultConfig extends Config (
          addrBits = Dump("MEM_ADDR_BITS", site(PAddrBits)),
          idBits = Dump("MEM_ID_BITS", site(MIFTagBits)))
      }
+      case HastiKey => HastiParameters(
+                        dataBits = site(XLen),
+                        addrBits = site(PAddrBits))
      //Params used by all caches
      case NSets => findBy(CacheName)
      case NWays => findBy(CacheName)
--- a/2
+++ b/2