fixes for priv-1.9 changes
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5e793427eb
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@ -21,8 +21,8 @@ class CacheFillTest(implicit p: Parameters) extends GroundTest()(p)
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io.mem.acquire.valid := active && !inflight
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io.mem.acquire.bits := Mux(state === s_prefetch,
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GetPrefetch(xact_id, req_block),
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GetBlock(xact_id, req_block))
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GetPrefetch(xact_id, UInt(memStartBlock) + req_block),
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GetBlock(xact_id, UInt(memStartBlock) + req_block))
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io.mem.grant.ready := active
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when (io.mem.acquire.fire()) {
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@ -87,7 +87,7 @@ class DmaStreamTest(implicit p: Parameters) extends GroundTest()(p)
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io.mem <> frontend.io.mem
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val status_reg = Module(new DmaStatusReg)
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status_reg.io.csr <> io.csr
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//status_reg.io.csr <> io.csr
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status_reg.io.incr_outstanding := frontend.io.incr_outstanding
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val cache_addr_base = Mux(state === s_setup_req, UInt(conf.source), UInt(conf.dest))
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@ -161,7 +161,7 @@ class DmaTest(implicit p: Parameters) extends GroundTest()(p)
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io.mem <> frontend.io.mem
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val status_reg = Module(new DmaStatusReg)
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status_reg.io.csr <> io.csr
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//status_reg.io.csr <> io.csr
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status_reg.io.incr_outstanding := frontend.io.incr_outstanding
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val dma_done = !frontend.io.busy && !status_reg.io.xact_outstanding
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@ -11,7 +11,7 @@ case object NGenerators extends Field[Int]
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case object GenerateUncached extends Field[Boolean]
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case object GenerateCached extends Field[Boolean]
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case object MaxGenerateRequests extends Field[Int]
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case object GeneratorStartAddress extends Field[Int]
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case object GeneratorStartAddress extends Field[BigInt]
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trait HasGeneratorParams {
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implicit val p: Parameters
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@ -25,7 +25,7 @@ trait HasGeneratorParams {
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val genWordBytes = genWordBits / 8
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val wordOffset = log2Up(genWordBytes)
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require(startAddress % genWordBytes == 0)
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require(startAddress % BigInt(genWordBytes) == 0)
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}
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class UncachedTileLinkGenerator(id: Int)
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@ -6,11 +6,12 @@ import junctions._
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import cde.Parameters
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abstract class NastiTest(implicit val p: Parameters) extends Module
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with HasNastiParameters with HasMIFParameters {
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with HasNastiParameters with HasMIFParameters with HasAddrMapParameters {
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val io = new Bundle {
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val finished = Bool(OUTPUT)
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val mem = new NastiIO
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}
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val memStart = addrMap("mem").start
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}
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class NastiBlockTest(implicit p: Parameters) extends NastiTest()(p) {
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@ -29,7 +30,7 @@ class NastiBlockTest(implicit p: Parameters) extends NastiTest()(p) {
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io.mem.aw.valid := (state === s_write_req) && !addr_sent
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io.mem.aw.bits := NastiWriteAddressChannel(
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id = UInt(0),
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addr = UInt(0),
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addr = UInt(memStart),
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len = UInt(mifDataBeats - 1),
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size = UInt(log2Up(mifDataBits / 8)))
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@ -43,7 +44,7 @@ class NastiBlockTest(implicit p: Parameters) extends NastiTest()(p) {
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io.mem.ar.valid := (state === s_read_req)
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io.mem.ar.bits := NastiReadAddressChannel(
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id = UInt(1),
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addr = UInt(0),
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addr = UInt(memStart),
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len = UInt(mifDataBeats - 1),
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size = UInt(log2Up(mifDataBits / 8)))
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@ -77,7 +78,7 @@ class NastiSmallTest(implicit p: Parameters) extends NastiTest()(p) {
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io.mem.aw.valid := (state === s_write_addr)
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io.mem.aw.bits := NastiWriteAddressChannel(
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id = UInt(0),
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addr = UInt(0x20C),
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addr = UInt(memStart + 0x20C),
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len = UInt(0),
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size = UInt("b010"))
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@ -89,7 +90,7 @@ class NastiSmallTest(implicit p: Parameters) extends NastiTest()(p) {
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io.mem.ar.valid := (state === s_read_req)
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io.mem.ar.bits := NastiReadAddressChannel(
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id = UInt(1),
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addr = UInt(0x20C),
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addr = UInt(memStart + 0x20C),
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len = UInt(0),
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size = UInt("b010"))
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@ -15,6 +15,8 @@ class RegressionIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
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abstract class Regression(implicit val p: Parameters)
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extends Module with HasTileLinkParameters with HasAddrMapParameters {
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val memStart = addrMap("mem").start
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val memStartBlock = memStart >> p(CacheBlockOffsetBits)
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val io = new RegressionIO
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}
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@ -43,13 +45,13 @@ class IOGetAfterPutBlockRegression(implicit p: Parameters) extends Regression()(
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io.mem.acquire.valid := !put_sent && started
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io.mem.acquire.bits := PutBlock(
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client_xact_id = UInt(0),
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addr_block = UInt(0),
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addr_block = UInt(memStartBlock),
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addr_beat = put_beat,
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data = UInt(0))
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io.mem.grant.ready := Bool(true)
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io.cache.req.valid := !get_sent && started
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io.cache.req.bits.addr := UInt(addrMap("conf:devicetree").start)
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io.cache.req.bits.addr := UInt(addrMap("io:int:bootrom").start)
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io.cache.req.bits.typ := MT_W
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io.cache.req.bits.cmd := M_XRD
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io.cache.req.bits.tag := UInt(0)
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@ -86,7 +88,7 @@ class PutBlockMergeRegression(implicit p: Parameters)
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val l2params = p.alterPartial({ case CacheName => "L2Bank" })
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val nSets = l2params(NSets)
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val addr_blocks = Vec(UInt(0), UInt(0), UInt(nSets))
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val addr_blocks = Vec(Seq(0, 0, nSets).map(num => UInt(num + memStartBlock)))
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val nSteps = addr_blocks.size
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val (acq_beat, acq_done) = Counter(io.mem.acquire.fire(), tlDataBeats)
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val (send_cnt, send_done) = Counter(acq_done, nSteps)
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@ -121,7 +123,7 @@ class NoAllocPutHitRegression(implicit p: Parameters) extends Regression()(p) {
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val (put_beat, put_done) = Counter(io.mem.acquire.fire() && acq.hasData(), tlDataBeats)
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val acked = Reg(init = UInt(0, tlDataBeats + 2))
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val addr_block = UInt(2)
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val addr_block = UInt(memStartBlock + 2)
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val test_data = UInt(0x3446)
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val prefetch_acq = GetPrefetch(
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@ -183,7 +185,7 @@ class RepeatedNoAllocPutRegression(implicit p: Parameters) extends Regression()(
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io.mem.acquire.valid := sending
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io.mem.acquire.bits := PutBlock(
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client_xact_id = req_cnt,
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addr_block = UInt(5),
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addr_block = UInt(memStartBlock + 5),
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addr_beat = put_beat,
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data = Cat(req_cnt, UInt(0, 8)),
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alloc = Bool(false))
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@ -217,14 +219,14 @@ class WriteMaskedPutBlockRegression(implicit p: Parameters) extends Regression()
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val put_acq = PutBlock(
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client_xact_id = UInt(0),
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addr_block = UInt(7),
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addr_block = UInt(memStartBlock + 7),
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addr_beat = put_beat,
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data = Mux(put_beat(0) === stage, put_data, UInt(0)),
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wmask = Mux(put_beat(0) === stage, Acquire.fullWriteMask, Bits(0)))
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val get_acq = GetBlock(
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client_xact_id = UInt(0),
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addr_block = UInt(6) + stage)
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addr_block = UInt(memStartBlock + 6) + stage)
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io.mem.acquire.valid := (state === s_put_send || state === s_get_send)
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io.mem.acquire.bits := Mux(state === s_get_send, get_acq, put_acq)
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@ -272,8 +274,8 @@ class PrefetchHitRegression(implicit p: Parameters) extends Regression()(p) {
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val acked = Reg(init = UInt(0, nPrefetches))
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val acq_bits = Vec(
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PutPrefetch(client_xact_id = UInt(0), addr_block = UInt(12)),
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GetPrefetch(client_xact_id = UInt(1), addr_block = UInt(12)))
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PutPrefetch(client_xact_id = UInt(0), addr_block = UInt(memStartBlock + 12)),
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GetPrefetch(client_xact_id = UInt(1), addr_block = UInt(memStartBlock + 12)))
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io.mem.acquire.valid := sending
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io.mem.acquire.bits := acq_bits(pf_cnt)
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@ -310,7 +312,7 @@ class SequentialSameIdGetRegression(implicit p: Parameters) extends Regression()
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io.mem.acquire.valid := sending
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io.mem.acquire.bits := Get(
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client_xact_id = UInt(0),
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addr_block = UInt(9),
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addr_block = UInt(memStartBlock + 9),
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addr_beat = send_cnt)
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io.mem.grant.ready := !finished
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@ -331,7 +333,7 @@ class WritebackRegression(implicit p: Parameters) extends Regression()(p) {
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val nSets = l2params(NSets)
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val nWays = l2params(NWays)
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val addr_blocks = Vec.tabulate(nWays + 1) { i => UInt(i * nSets) }
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val addr_blocks = Vec.tabulate(nWays + 1) { i => UInt(memStartBlock + i * nSets) }
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val data = Vec.tabulate(nWays + 1) { i => UInt((i + 1) * 1423) }
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val (put_beat, put_done) = Counter(
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@ -388,14 +390,14 @@ class PutBeforePutBlockRegression(implicit p: Parameters) extends Regression()(p
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val put_acquire = Put(
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client_xact_id = UInt(0),
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addr_block = UInt(0),
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addr_block = UInt(memStartBlock),
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addr_beat = UInt(0),
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data = UInt(0),
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wmask = UInt((1 << 8) - 1))
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val put_block_acquire = PutBlock(
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client_xact_id = UInt(1),
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addr_block = UInt(1),
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addr_block = UInt(memStartBlock + 1),
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addr_beat = put_block_beat,
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data = UInt(0))
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@ -3,7 +3,7 @@ package groundtest
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import Chisel._
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import rocket._
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import uncore._
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import junctions.{SmiIO, ParameterizedBundle}
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import junctions._
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import scala.util.Random
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import cde.{Parameters, Field}
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@ -75,61 +75,19 @@ class DummyPTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
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}
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}
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class CSRHandler(implicit val p: Parameters) extends Module {
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private val csrDataBits = 64
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private val csrAddrBits = 12
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val io = new Bundle {
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val finished = Bool(INPUT)
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val csr = new SmiIO(csrDataBits, csrAddrBits).flip
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val rocc = new RoCCCSRs
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}
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val csr_resp_valid = Reg(Bool()) // Don't reset
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val csr_resp_data = Reg(UInt(width = csrDataBits))
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io.csr.req.ready := Bool(true)
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io.csr.resp.valid := csr_resp_valid
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io.csr.resp.bits := csr_resp_data
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val req = io.csr.req.bits
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val csr_list = p(GroundTestCSRs)
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val rocc_csr = csr_list.map(num => req.addr === UInt(num))
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.foldLeft(Bool(false))(_ || _)
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val default_csr_rdata = Mux(req.addr === UInt(CSRs.mtohost), io.finished, req.data)
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val csr_rdata = csr_list.zipWithIndex.foldLeft(default_csr_rdata) {
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(res, pair) => pair match {
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case (csrnum, i) => Mux(
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req.addr === UInt(csrnum), io.rocc.rdata(i), res)
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}
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}
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when (io.csr.req.fire()) {
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csr_resp_valid := Bool(true)
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csr_resp_data := csr_rdata
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}
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when (io.csr.resp.fire()) {
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csr_resp_valid := Bool(false)
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}
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io.rocc.waddr := req.addr
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io.rocc.wdata := req.data
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io.rocc.wen := io.csr.req.valid && req.rw && rocc_csr
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}
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class GroundTestIO(implicit p: Parameters) extends ParameterizedBundle()(p) {
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val cache = new HellaCacheIO
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val mem = new ClientUncachedTileLinkIO
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val dma = new DmaIO
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val ptw = new TLBPTWIO
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val csr = (new RoCCCSRs).flip
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val finished = Bool(OUTPUT)
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}
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abstract class GroundTest(implicit val p: Parameters) extends Module {
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abstract class GroundTest(implicit val p: Parameters) extends Module
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with HasAddrMapParameters {
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val io = new GroundTestIO
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val memStart = addrMap("mem").start
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val memStartBlock = memStart >> p(CacheBlockOffsetBits)
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def disablePorts(mem: Boolean = true,
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cache: Boolean = true,
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@ -147,11 +105,36 @@ abstract class GroundTest(implicit val p: Parameters) extends Module {
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}
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}
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class GroundTestFinisher(implicit p: Parameters) extends TLModule()(p) {
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val io = new Bundle {
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val finished = Bool(INPUT)
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val mem = new ClientUncachedTileLinkIO
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}
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val addrBits = p(PAddrBits)
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val offsetBits = tlBeatAddrBits + tlByteAddrBits
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val tohostAddr = UInt("h80001000")
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val s_idle :: s_write_tohost :: s_wait :: Nil = Enum(Bits(), 3)
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val state = Reg(init = s_idle)
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when (state === s_idle && io.finished) { state := s_write_tohost }
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when (io.mem.acquire.fire()) { state := s_wait }
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io.mem.acquire.valid := (state === s_write_tohost)
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io.mem.acquire.bits := Put(
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client_xact_id = UInt(0),
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addr_block = tohostAddr(addrBits - 1, offsetBits),
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addr_beat = tohostAddr(offsetBits - 1, tlByteAddrBits),
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data = UInt(1),
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wmask = SInt(-1, 8).asUInt)
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io.mem.grant.ready := (state === s_wait)
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}
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class GroundTestTile(id: Int, resetSignal: Bool)
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(implicit val p: Parameters) extends Tile(resetSignal)(p) {
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val test = p(BuildGroundTest)(id, dcacheParams)
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io.uncached.head <> test.io.mem
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val dcache = Module(new HellaCache()(dcacheParams))
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val dcacheIF = Module(new SimpleHellaCacheIF()(dcacheParams))
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@ -159,14 +142,15 @@ class GroundTestTile(id: Int, resetSignal: Bool)
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dcache.io.cpu <> dcacheIF.io.cache
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io.cached.head <> dcache.io.mem
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val csr = Module(new CSRHandler)
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csr.io.finished := test.io.finished
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csr.io.csr <> io.host.csr
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if (!p(GroundTestCSRs).isEmpty) {
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test.io.csr <> csr.io.rocc
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}
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val ptw = Module(new DummyPTW(2))
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ptw.io.requestors(0) <> test.io.ptw
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ptw.io.requestors(1) <> dcache.io.ptw
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val finisher = Module(new GroundTestFinisher)
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finisher.io.finished := test.io.finished
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val memArb = Module(new ClientUncachedTileLinkIOArbiter(2))
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memArb.io.in(0) <> test.io.mem
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memArb.io.in(1) <> finisher.io.mem
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io.uncached.head <> memArb.io.out
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}
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