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fixes for priv-1.9 changes

This commit is contained in:
Howard Mao 2016-05-02 18:25:02 -07:00
parent 5e793427eb
commit 4b4e8f7f62
6 changed files with 66 additions and 79 deletions
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4
groundtest/src/main/scala/cachetest.scala
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@ -21,8 +21,8 @@ class CacheFillTest(implicit p: Parameters) extends GroundTest()(p)
io.mem.acquire.valid := active && !inflight
io.mem.acquire.bits := Mux(state === s_prefetch,
GetPrefetch(xact_id, req_block),
GetBlock(xact_id, req_block))
GetPrefetch(xact_id, UInt(memStartBlock) + req_block),
GetBlock(xact_id, UInt(memStartBlock) + req_block))
io.mem.grant.ready := active
when (io.mem.acquire.fire()) {

4
groundtest/src/main/scala/dmatest.scala
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@ -87,7 +87,7 @@ class DmaStreamTest(implicit p: Parameters) extends GroundTest()(p)
io.mem <> frontend.io.mem
val status_reg = Module(new DmaStatusReg)
status_reg.io.csr <> io.csr
//status_reg.io.csr <> io.csr
status_reg.io.incr_outstanding := frontend.io.incr_outstanding
val cache_addr_base = Mux(state === s_setup_req, UInt(conf.source), UInt(conf.dest))
@ -161,7 +161,7 @@ class DmaTest(implicit p: Parameters) extends GroundTest()(p)
io.mem <> frontend.io.mem
val status_reg = Module(new DmaStatusReg)
status_reg.io.csr <> io.csr
//status_reg.io.csr <> io.csr
status_reg.io.incr_outstanding := frontend.io.incr_outstanding
val dma_done = !frontend.io.busy && !status_reg.io.xact_outstanding

4
groundtest/src/main/scala/generator.scala
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@ -11,7 +11,7 @@ case object NGenerators extends Field[Int]
case object GenerateUncached extends Field[Boolean]
case object GenerateCached extends Field[Boolean]
case object MaxGenerateRequests extends Field[Int]
case object GeneratorStartAddress extends Field[Int]
case object GeneratorStartAddress extends Field[BigInt]
trait HasGeneratorParams {
implicit val p: Parameters
@ -25,7 +25,7 @@ trait HasGeneratorParams {
val genWordBytes = genWordBits / 8
val wordOffset = log2Up(genWordBytes)
require(startAddress % genWordBytes == 0)
require(startAddress % BigInt(genWordBytes) == 0)
}
class UncachedTileLinkGenerator(id: Int)

11
groundtest/src/main/scala/nastitest.scala
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@ -6,11 +6,12 @@ import junctions._
import cde.Parameters
abstract class NastiTest(implicit val p: Parameters) extends Module
with HasNastiParameters with HasMIFParameters {
with HasNastiParameters with HasMIFParameters with HasAddrMapParameters {
val io = new Bundle {
val finished = Bool(OUTPUT)
val mem = new NastiIO
}
val memStart = addrMap("mem").start
}
class NastiBlockTest(implicit p: Parameters) extends NastiTest()(p) {
@ -29,7 +30,7 @@ class NastiBlockTest(implicit p: Parameters) extends NastiTest()(p) {
io.mem.aw.valid := (state === s_write_req) && !addr_sent
io.mem.aw.bits := NastiWriteAddressChannel(
id = UInt(0),
addr = UInt(0),
addr = UInt(memStart),
len = UInt(mifDataBeats - 1),
size = UInt(log2Up(mifDataBits / 8)))
@ -43,7 +44,7 @@ class NastiBlockTest(implicit p: Parameters) extends NastiTest()(p) {
io.mem.ar.valid := (state === s_read_req)
io.mem.ar.bits := NastiReadAddressChannel(
id = UInt(1),
addr = UInt(0),
addr = UInt(memStart),
len = UInt(mifDataBeats - 1),
size = UInt(log2Up(mifDataBits / 8)))
@ -77,7 +78,7 @@ class NastiSmallTest(implicit p: Parameters) extends NastiTest()(p) {
io.mem.aw.valid := (state === s_write_addr)
io.mem.aw.bits := NastiWriteAddressChannel(
id = UInt(0),
addr = UInt(0x20C),
addr = UInt(memStart + 0x20C),
len = UInt(0),
size = UInt("b010"))
@ -89,7 +90,7 @@ class NastiSmallTest(implicit p: Parameters) extends NastiTest()(p) {
io.mem.ar.valid := (state === s_read_req)
io.mem.ar.bits := NastiReadAddressChannel(
id = UInt(1),
addr = UInt(0x20C),
addr = UInt(memStart + 0x20C),
len = UInt(0),
size = UInt("b010"))

28
groundtest/src/main/scala/regression.scala
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@ -15,6 +15,8 @@ class RegressionIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
abstract class Regression(implicit val p: Parameters)
extends Module with HasTileLinkParameters with HasAddrMapParameters {
val memStart = addrMap("mem").start
val memStartBlock = memStart >> p(CacheBlockOffsetBits)
val io = new RegressionIO
}
@ -43,13 +45,13 @@ class IOGetAfterPutBlockRegression(implicit p: Parameters) extends Regression()(
io.mem.acquire.valid := !put_sent && started
io.mem.acquire.bits := PutBlock(
client_xact_id = UInt(0),
addr_block = UInt(0),
addr_block = UInt(memStartBlock),
addr_beat = put_beat,
data = UInt(0))
io.mem.grant.ready := Bool(true)
io.cache.req.valid := !get_sent && started
io.cache.req.bits.addr := UInt(addrMap("conf:devicetree").start)
io.cache.req.bits.addr := UInt(addrMap("io:int:bootrom").start)
io.cache.req.bits.typ := MT_W
io.cache.req.bits.cmd := M_XRD
io.cache.req.bits.tag := UInt(0)
@ -86,7 +88,7 @@ class PutBlockMergeRegression(implicit p: Parameters)
val l2params = p.alterPartial({ case CacheName => "L2Bank" })
val nSets = l2params(NSets)
val addr_blocks = Vec(UInt(0), UInt(0), UInt(nSets))
val addr_blocks = Vec(Seq(0, 0, nSets).map(num => UInt(num + memStartBlock)))
val nSteps = addr_blocks.size
val (acq_beat, acq_done) = Counter(io.mem.acquire.fire(), tlDataBeats)
val (send_cnt, send_done) = Counter(acq_done, nSteps)
@ -121,7 +123,7 @@ class NoAllocPutHitRegression(implicit p: Parameters) extends Regression()(p) {
val (put_beat, put_done) = Counter(io.mem.acquire.fire() && acq.hasData(), tlDataBeats)
val acked = Reg(init = UInt(0, tlDataBeats + 2))
val addr_block = UInt(2)
val addr_block = UInt(memStartBlock + 2)
val test_data = UInt(0x3446)
val prefetch_acq = GetPrefetch(
@ -183,7 +185,7 @@ class RepeatedNoAllocPutRegression(implicit p: Parameters) extends Regression()(
io.mem.acquire.valid := sending
io.mem.acquire.bits := PutBlock(
client_xact_id = req_cnt,
addr_block = UInt(5),
addr_block = UInt(memStartBlock + 5),
addr_beat = put_beat,
data = Cat(req_cnt, UInt(0, 8)),
alloc = Bool(false))
@ -217,14 +219,14 @@ class WriteMaskedPutBlockRegression(implicit p: Parameters) extends Regression()
val put_acq = PutBlock(
client_xact_id = UInt(0),
addr_block = UInt(7),
addr_block = UInt(memStartBlock + 7),
addr_beat = put_beat,
data = Mux(put_beat(0) === stage, put_data, UInt(0)),
wmask = Mux(put_beat(0) === stage, Acquire.fullWriteMask, Bits(0)))
val get_acq = GetBlock(
client_xact_id = UInt(0),
addr_block = UInt(6) + stage)
addr_block = UInt(memStartBlock + 6) + stage)
io.mem.acquire.valid := (state === s_put_send || state === s_get_send)
io.mem.acquire.bits := Mux(state === s_get_send, get_acq, put_acq)
@ -272,8 +274,8 @@ class PrefetchHitRegression(implicit p: Parameters) extends Regression()(p) {
val acked = Reg(init = UInt(0, nPrefetches))
val acq_bits = Vec(
PutPrefetch(client_xact_id = UInt(0), addr_block = UInt(12)),
GetPrefetch(client_xact_id = UInt(1), addr_block = UInt(12)))
PutPrefetch(client_xact_id = UInt(0), addr_block = UInt(memStartBlock + 12)),
GetPrefetch(client_xact_id = UInt(1), addr_block = UInt(memStartBlock + 12)))
io.mem.acquire.valid := sending
io.mem.acquire.bits := acq_bits(pf_cnt)
@ -310,7 +312,7 @@ class SequentialSameIdGetRegression(implicit p: Parameters) extends Regression()
io.mem.acquire.valid := sending
io.mem.acquire.bits := Get(
client_xact_id = UInt(0),
addr_block = UInt(9),
addr_block = UInt(memStartBlock + 9),
addr_beat = send_cnt)
io.mem.grant.ready := !finished
@ -331,7 +333,7 @@ class WritebackRegression(implicit p: Parameters) extends Regression()(p) {
val nSets = l2params(NSets)
val nWays = l2params(NWays)
val addr_blocks = Vec.tabulate(nWays + 1) { i => UInt(i * nSets) }
val addr_blocks = Vec.tabulate(nWays + 1) { i => UInt(memStartBlock + i * nSets) }
val data = Vec.tabulate(nWays + 1) { i => UInt((i + 1) * 1423) }
val (put_beat, put_done) = Counter(
@ -388,14 +390,14 @@ class PutBeforePutBlockRegression(implicit p: Parameters) extends Regression()(p
val put_acquire = Put(
client_xact_id = UInt(0),
addr_block = UInt(0),
addr_block = UInt(memStartBlock),
addr_beat = UInt(0),
data = UInt(0),
wmask = UInt((1 << 8) - 1))
val put_block_acquire = PutBlock(
client_xact_id = UInt(1),
addr_block = UInt(1),
addr_block = UInt(memStartBlock + 1),
addr_beat = put_block_beat,
data = UInt(0))

94
groundtest/src/main/scala/tile.scala
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@ -3,7 +3,7 @@ package groundtest
import Chisel._
import rocket._
import uncore._
import junctions.{SmiIO, ParameterizedBundle}
import junctions._
import scala.util.Random
import cde.{Parameters, Field}
@ -75,61 +75,19 @@ class DummyPTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
}
}
class CSRHandler(implicit val p: Parameters) extends Module {
private val csrDataBits = 64
private val csrAddrBits = 12
val io = new Bundle {
val finished = Bool(INPUT)
val csr = new SmiIO(csrDataBits, csrAddrBits).flip
val rocc = new RoCCCSRs
}
val csr_resp_valid = Reg(Bool()) // Don't reset
val csr_resp_data = Reg(UInt(width = csrDataBits))
io.csr.req.ready := Bool(true)
io.csr.resp.valid := csr_resp_valid
io.csr.resp.bits := csr_resp_data
val req = io.csr.req.bits
val csr_list = p(GroundTestCSRs)
val rocc_csr = csr_list.map(num => req.addr === UInt(num))
.foldLeft(Bool(false))(_ || _)
val default_csr_rdata = Mux(req.addr === UInt(CSRs.mtohost), io.finished, req.data)
val csr_rdata = csr_list.zipWithIndex.foldLeft(default_csr_rdata) {
(res, pair) => pair match {
case (csrnum, i) => Mux(
req.addr === UInt(csrnum), io.rocc.rdata(i), res)
}
}
when (io.csr.req.fire()) {
csr_resp_valid := Bool(true)
csr_resp_data := csr_rdata
}
when (io.csr.resp.fire()) {
csr_resp_valid := Bool(false)
}
io.rocc.waddr := req.addr
io.rocc.wdata := req.data
io.rocc.wen := io.csr.req.valid && req.rw && rocc_csr
}
class GroundTestIO(implicit p: Parameters) extends ParameterizedBundle()(p) {
val cache = new HellaCacheIO
val mem = new ClientUncachedTileLinkIO
val dma = new DmaIO
val ptw = new TLBPTWIO
val csr = (new RoCCCSRs).flip
val finished = Bool(OUTPUT)
}
abstract class GroundTest(implicit val p: Parameters) extends Module {
abstract class GroundTest(implicit val p: Parameters) extends Module
with HasAddrMapParameters {
val io = new GroundTestIO
val memStart = addrMap("mem").start
val memStartBlock = memStart >> p(CacheBlockOffsetBits)
def disablePorts(mem: Boolean = true,
cache: Boolean = true,
@ -147,11 +105,36 @@ abstract class GroundTest(implicit val p: Parameters) extends Module {
}
}
class GroundTestFinisher(implicit p: Parameters) extends TLModule()(p) {
val io = new Bundle {
val finished = Bool(INPUT)
val mem = new ClientUncachedTileLinkIO
}
val addrBits = p(PAddrBits)
val offsetBits = tlBeatAddrBits + tlByteAddrBits
val tohostAddr = UInt("h80001000")
val s_idle :: s_write_tohost :: s_wait :: Nil = Enum(Bits(), 3)
val state = Reg(init = s_idle)
when (state === s_idle && io.finished) { state := s_write_tohost }
when (io.mem.acquire.fire()) { state := s_wait }
io.mem.acquire.valid := (state === s_write_tohost)
io.mem.acquire.bits := Put(
client_xact_id = UInt(0),
addr_block = tohostAddr(addrBits - 1, offsetBits),
addr_beat = tohostAddr(offsetBits - 1, tlByteAddrBits),
data = UInt(1),
wmask = SInt(-1, 8).asUInt)
io.mem.grant.ready := (state === s_wait)
}
class GroundTestTile(id: Int, resetSignal: Bool)
(implicit val p: Parameters) extends Tile(resetSignal)(p) {
val test = p(BuildGroundTest)(id, dcacheParams)
io.uncached.head <> test.io.mem
val dcache = Module(new HellaCache()(dcacheParams))
val dcacheIF = Module(new SimpleHellaCacheIF()(dcacheParams))
@ -159,14 +142,15 @@ class GroundTestTile(id: Int, resetSignal: Bool)
dcache.io.cpu <> dcacheIF.io.cache
io.cached.head <> dcache.io.mem
val csr = Module(new CSRHandler)
csr.io.finished := test.io.finished
csr.io.csr <> io.host.csr
if (!p(GroundTestCSRs).isEmpty) {
test.io.csr <> csr.io.rocc
}
val ptw = Module(new DummyPTW(2))
ptw.io.requestors(0) <> test.io.ptw
ptw.io.requestors(1) <> dcache.io.ptw
val finisher = Module(new GroundTestFinisher)
finisher.io.finished := test.io.finished
val memArb = Module(new ClientUncachedTileLinkIOArbiter(2))
memArb.io.in(0) <> test.io.mem
memArb.io.in(1) <> finisher.io.mem
io.uncached.head <> memArb.io.out
}