changes to match junctions no-mmio-base
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@ -291,7 +291,7 @@ class TileLinkRecursiveInterconnect(
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addrmap.zip(realAddrMap).zip(xbar.io.out).zipWithIndex.foreach {
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case (((entry, (start, size)), xbarOut), i) => {
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entry.region match {
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case MemSize(_, _) =>
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case MemSize(_, _, _) =>
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io.out(outInd) <> xbarOut
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outInd += 1
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case MemSubmap(_, submap) =>
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@ -1,7 +1,7 @@
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package uncore
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import Chisel._
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import junctions.{SmiIO, MMIOBase}
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import junctions.SmiIO
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import cde.Parameters
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import scala.collection.mutable.HashMap
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import scala.collection.mutable.ArrayBuffer
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